公开(公告)号：US20110320751A1

公开(公告)日：2011-12-29

申请号：US12823370

申请日：2010-06-25

申请人： Feng Wang ,  Shiqun Gu ,  Matthew Michael Nowak

发明人： Feng Wang ,  Shiqun Gu ,  Matthew Michael Nowak

IPC分类号： G06F12/06

CPC分类号： G06F13/1652 ,  G06F13/1684 ,  Y02D10/14

摘要： In a particular embodiment, a dynamic interleaving system changes the number of interleaving channels of a multi-channel memory based on a detected level of bandwidth requests from a plurality of master ports to a plurality of slave ports. At a low level of bandwidth requests, the number of interleaving channels is reduced.

摘要翻译： 在特定实施例中，动态交织系统基于从多个主端口到多个从端口的检测到的带宽请求的级别来改变多信道存储器的交织信道的数量。 在低等级的带宽请求下，减少了交织信道的数量。

公开(公告)号：US08380940B2

公开(公告)日：2013-02-19

申请号：US12823515

申请日：2010-06-25

申请人： Feng Wang ,  Shiqun Gu ,  Matthew Michael Nowak

发明人： Feng Wang ,  Shiqun Gu ,  Matthew Michael Nowak

IPC分类号： G06F12/06

CPC分类号： G06F13/1663

摘要： A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.

摘要翻译： 公开了一种多通道多端口存储器。 在特定实施例中，多通道存储器包括响应于多个存储器控制器的多个通道。 多通道存储器还可以包括可由第一组多个通道访问的第一多端口多存储体结构和可由第二组多个通道访问的第二多端口多存储体结构。

公开(公告)号：US08230239B2

公开(公告)日：2012-07-24

申请号：US12417309

申请日：2009-04-02

申请人： Feng Wang ,  Shiqun Gu

发明人： Feng Wang ,  Shiqun Gu

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F12/00 ,  G11C5/14

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

摘要： A memory power management system and method supporting multiple power modes for powering memory channels. The power management system can include a memory controller that controls the memory channel; a throughput detector that detects a requested throughput of the memory channel; a power control logic that determines a desired power mode corresponding to the requested throughput; and a power control device that supplies a desired voltage of the desired power mode to the memory channel. The power management system can include multiple memory controllers for controlling a multi-channel memory independently. The method includes detecting a requested throughput for the memory channel; determining a desired voltage related to the requested throughput; requesting the desired voltage from a voltage device; and applying the desired voltage to the memory channel. In some embodiments, the method only applies the desired voltage if it does not change for a threshold time duration.

摘要翻译： 一种支持多种功率模式以为存储器通道供电的存储器电源管理系统和方法。 电源管理系统可以包括控制存储器通道的存储器控​​制器; 吞吐量检测器，其检测所述存储器通道的所请求的吞吐量; 功率控制逻辑，其确定对应于所请求的吞吐量的期望功率模式; 以及功率控制装置，其将期望的功率模式的期望电压提供给存储器通道。 电源管理系统可以包括用于独立地控制多通道存储器的多个存储器控制器。 所述方法包括检测所述存储器通道的所请求的吞吐量; 确定与所请求的吞吐量相关的期望电压; 从电压装置请求所需的电压; 以及将所需的电压施加到存储器通道。 在一些实施例中，如果在阈值持续时间内没有改变，该方法仅施加期望的电压。

公开(公告)号：US09268720B2

公开(公告)日：2016-02-23

申请号：US12872282

申请日：2010-08-31

申请人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

发明人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

IPC分类号： G06F13/16 ,  G06F12/06

CPC分类号： G06F13/1647 ,  G06F12/0607 ,  G06F13/1642 ,  G06F13/1657 ,  G06F2213/0064

摘要： A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

摘要翻译： 多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。 内存通道的访问由内存控制器控制。 总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。 如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。 因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。

公开(公告)号：US20120054455A1

公开(公告)日：2012-03-01

申请号：US12872458

申请日：2010-08-31

申请人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

发明人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

IPC分类号： G06F12/06

CPC分类号： G06F13/1647 ,  G06F12/0607

摘要： A non-uniform interleaving scheme in a multiple channel DRAM system comprises associating memory data with a memory address, associating address zones to predetermined ranges of memory addresses and associating predetermined interleaving granularities with the address zones. Memory data is interleaved across two or more memory channels such that a predetermined interleaving granularity is applied to each address zone.

摘要翻译： 多通道DRAM系统中的非均匀交织方案包括将存储器数据与存储器地址相关联，将地址区域与预定范围的存储器地址相关联，并将预定的交织粒度与地址区域相关联。 存储器数据在两个或更多个存储器通道之间交错，使得预定的交织粒度被应用于每个地址区。

公开(公告)号：US20110320698A1

公开(公告)日：2011-12-29

申请号：US12823515

申请日：2010-06-25

申请人： Feng Wang ,  Shiqun Gu ,  Matthew Michael Nowak

发明人： Feng Wang ,  Shiqun Gu ,  Matthew Michael Nowak

IPC分类号： G06F12/00

CPC分类号： G06F13/1663

摘要： A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.

摘要翻译： 公开了一种多通道多端口存储器。 在特定实施例中，多通道存储器包括响应于多个存储器控制器的多个通道。 多通道存储器还可以包括可由第一组多个通道访问的第一多端口多存储体结构和可由第二组多个通道访问的第二多端口多存储体结构。

公开(公告)号：US20120054423A1

公开(公告)日：2012-03-01

申请号：US12872282

申请日：2010-08-31

申请人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

发明人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

IPC分类号： G06F12/02

CPC分类号： G06F13/1647 ,  G06F12/0607 ,  G06F13/1642 ,  G06F13/1657 ,  G06F2213/0064

摘要： A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

摘要翻译： 多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。 内存通道的访问由内存控制器控制。 总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。 如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。 因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。

公开(公告)号：US20100257379A1

公开(公告)日：2010-10-07

申请号：US12417309

申请日：2009-04-02

申请人： Feng Wang ,  Shiqun Gu

发明人： Feng Wang ,  Shiqun Gu

IPC分类号： G06F1/00

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

摘要： A memory power management system and method supporting multiple power modes for powering memory channels. The power management system can include a memory controller that controls the memory channel; a throughput detector that detects a requested throughput of the memory channel; a power control logic that determines a desired power mode corresponding to the requested throughput; and a power control device that supplies a desired voltage of the desired power mode to the memory channel. The power management system can include multiple memory controllers for controlling a multi-channel memory independently. The method includes detecting a requested throughput for the memory channel; determining a desired voltage related to the requested throughput; requesting the desired voltage from a voltage device; and applying the desired voltage to the memory channel. In some embodiments, the method only applies the desired voltage if it does not change for a threshold time duration.

摘要翻译： 一种支持多种功率模式以为存储器通道供电的存储器电源管理系统和方法。 电源管理系统可以包括控制存储器通道的存储器控​​制器; 吞吐量检测器，其检测所述存储器通道的所请求的吞吐量; 功率控制逻辑，其确定对应于所请求的吞吐量的期望功率模式; 以及功率控制装置，其将期望的功率模式的期望电压提供给存储器通道。 电源管理系统可以包括用于独立地控制多通道存储器的多个存储器控制器。 所述方法包括检测所述存储器通道的所请求的吞吐量; 确定与所请求的吞吐量相关的期望电压; 从电压装置请求所需的电压; 以及将所需的电压施加到存储器通道。 在一些实施例中，如果在阈值持续时间内没有改变，该方法仅施加期望的电压。

公开(公告)号：US11309722B2

公开(公告)日：2022-04-19

申请号：US17023378

申请日：2020-09-17

申请人： Xiaoxiao Liu ,  Feng Wang

发明人： Xiaoxiao Liu ,  Feng Wang

IPC分类号： H01M10/46 ,  H02J7/00 ,  H01M50/213 ,  H01M10/42 ,  H01M10/48

摘要： In the rechargeable battery with USB charging function, a cathode end of the battery body passes through the housing body and extends outside the housing body. One end of the circuit board is provided with an anode charging contact sheet, an anode discharging contact sheet and a ground contact sheet. Both the anode charging contact sheet and the anode discharging contact sheet are connected with an anode of the battery body. The anode charging contact sheet is connected with an anode pin of the male USB connector and the ground contact sheet is connected with a ground pin of the male USB connector when the male USB connector is inserted into a female USB connector; and the battery cover is provided with a conductive sheet which is electronically connected with the anode discharging contact sheet when the battery cover is connected with USB charging function.

公开(公告)号：US09444601B2

公开(公告)日：2016-09-13

申请号：US14364671

申请日：2012-04-18

申请人： Wei Zhang ,  Feng Wang ,  Dandan Guo ,  Ming Fang ,  Yao Wang

发明人： Wei Zhang ,  Feng Wang ,  Dandan Guo ,  Ming Fang ,  Yao Wang

IPC分类号： H04L5/00 ,  H04L25/06 ,  H04L1/18 ,  H04L29/08

CPC分类号： H04L5/0053 ,  H04L1/1812 ,  H04L1/1845 ,  H04L1/1874 ,  H04L1/1896 ,  H04L5/0007 ,  H04L25/067 ,  H04L67/2842

摘要： A method for Hybrid Automatic Repeat Request (HARQ) combination is disclosed. The method includes that: externally configured parameters relevant to HARQ combination are received, and an identifier ddr2switch of DDR2 switching is calculated to acquire addresses involved before and after the HARQ combination; it is determined, according to the parameters and the addresses involved before and after the HARQ combination, whether the HARQ combination is needed to be performed; and when it is determined that the HARQ combination is needed to be performed, data in a DDR2 are read and stored into a first data cache random access memory RAMA; and a HARQ combination calculation is performed, and the calculation result is stored into a second data cache random access memory RAMB. A device for HARQ combination is further disclosed. The technical solutions provided in the disclosure are based on a latest interference cancellation algorithm, greatly increase the success probability of decoding, saves the storage space of a DDR2 and improves the reading or writing efficiency.

摘要翻译： 公开了一种混合自动重传请求（HARQ）组合的方法。 该方法包括：接收与HARQ组合相关的外部配置参数，并且计算DDR2切换的标识符ddr2切换以获取HARQ组合之前和之后涉及的地址; 根据HARQ组合之前和之后的参数和地址确定是否需要执行HARQ组合; 并且当确定需要执行HARQ组合时，读取DDR2中的数据并将其存储到第一数据高速缓存随机存取存储器RAMA中; 并且执行HARQ组合计算，并且将计算结果存储到第二数据高速缓存随机存取存储器RAMB中。 还公开了一种用于HARQ组合的装置。 本公开提供的技术方案基于最新的干扰消除算法，大大提高了解码的成功概率，节省了DDR2的存储空间，提高了读写效率。