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公开(公告)号:US20120054423A1
公开(公告)日:2012-03-01
申请号:US12872282
申请日:2010-08-31
申请人: Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人: Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
IPC分类号: G06F12/02
CPC分类号: G06F13/1647 , G06F12/0607 , G06F13/1642 , G06F13/1657 , G06F2213/0064
摘要: A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.
摘要翻译: 多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。 内存通道的访问由内存控制器控制。 总线主机通过互连系统耦合到存储器控制器,并且存储器请求从总线主机传送到存储器控制器。 如果在存储器通道中检测到拥塞,则产生拥塞信号并将其发送到总线主机。 因此,基于拥塞信号,存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。
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公开(公告)号:US09268720B2
公开(公告)日:2016-02-23
申请号:US12872282
申请日:2010-08-31
申请人: Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人: Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
CPC分类号: G06F13/1647 , G06F12/0607 , G06F13/1642 , G06F13/1657 , G06F2213/0064
摘要: A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.
摘要翻译: 多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。 内存通道的访问由内存控制器控制。 总线主机通过互连系统耦合到存储器控制器,并且存储器请求从总线主机传送到存储器控制器。 如果在存储器通道中检测到拥塞,则产生拥塞信号并将其发送到总线主机。 因此,基于拥塞信号,存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。
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3.
公开(公告)号:US20120054455A1
公开(公告)日:2012-03-01
申请号:US12872458
申请日:2010-08-31
申请人: Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人: Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
IPC分类号: G06F12/06
CPC分类号: G06F13/1647 , G06F12/0607
摘要: A non-uniform interleaving scheme in a multiple channel DRAM system comprises associating memory data with a memory address, associating address zones to predetermined ranges of memory addresses and associating predetermined interleaving granularities with the address zones. Memory data is interleaved across two or more memory channels such that a predetermined interleaving granularity is applied to each address zone.
摘要翻译: 多通道DRAM系统中的非均匀交织方案包括将存储器数据与存储器地址相关联,将地址区域与预定范围的存储器地址相关联,并将预定的交织粒度与地址区域相关联。 存储器数据在两个或更多个存储器通道之间交错,使得预定的交织粒度被应用于每个地址区。
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公开(公告)号:US20110320751A1
公开(公告)日:2011-12-29
申请号:US12823370
申请日:2010-06-25
申请人: Feng Wang , Shiqun Gu , Matthew Michael Nowak
发明人: Feng Wang , Shiqun Gu , Matthew Michael Nowak
IPC分类号: G06F12/06
CPC分类号: G06F13/1652 , G06F13/1684 , Y02D10/14
摘要: In a particular embodiment, a dynamic interleaving system changes the number of interleaving channels of a multi-channel memory based on a detected level of bandwidth requests from a plurality of master ports to a plurality of slave ports. At a low level of bandwidth requests, the number of interleaving channels is reduced.
摘要翻译: 在特定实施例中,动态交织系统基于从多个主端口到多个从端口的检测到的带宽请求的级别来改变多信道存储器的交织信道的数量。 在低等级的带宽请求下,减少了交织信道的数量。
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公开(公告)号:US20110320698A1
公开(公告)日:2011-12-29
申请号:US12823515
申请日:2010-06-25
申请人: Feng Wang , Shiqun Gu , Matthew Michael Nowak
发明人: Feng Wang , Shiqun Gu , Matthew Michael Nowak
IPC分类号: G06F12/00
CPC分类号: G06F13/1663
摘要: A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.
摘要翻译: 公开了一种多通道多端口存储器。 在特定实施例中,多通道存储器包括响应于多个存储器控制器的多个通道。 多通道存储器还可以包括可由第一组多个通道访问的第一多端口多存储体结构和可由第二组多个通道访问的第二多端口多存储体结构。
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公开(公告)号:US08380940B2
公开(公告)日:2013-02-19
申请号:US12823515
申请日:2010-06-25
申请人: Feng Wang , Shiqun Gu , Matthew Michael Nowak
发明人: Feng Wang , Shiqun Gu , Matthew Michael Nowak
IPC分类号: G06F12/06
CPC分类号: G06F13/1663
摘要: A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.
摘要翻译: 公开了一种多通道多端口存储器。 在特定实施例中,多通道存储器包括响应于多个存储器控制器的多个通道。 多通道存储器还可以包括可由第一组多个通道访问的第一多端口多存储体结构和可由第二组多个通道访问的第二多端口多存储体结构。
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公开(公告)号:US08294240B2
公开(公告)日:2012-10-23
申请号:US12479885
申请日:2009-06-08
申请人: Matthew Michael Nowak , Shiqun Gu
发明人: Matthew Michael Nowak , Shiqun Gu
IPC分类号: H01L29/92
CPC分类号: H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/642 , H01L28/60 , H01L2223/6616 , H01L2223/6622 , H01L2224/0557 , H01L2224/06181 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2224/05552
摘要: A semiconductor die, having a substrate, includes a through silicon via. The through silicon via includes a decoupling capacitor having a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor. The decoupling capacitor is configured to provide local charge storage for components on the semiconductor die.
摘要翻译: 具有基板的半导体管芯包括硅通孔。 贯通硅通孔包括具有第一同轴导体,第二同轴导体和将第一同轴导体与第二同轴导体分离的同轴电介质的去耦电容器。 去耦电容器被配置为为半导体管芯上的部件提供局部电荷存储。
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公开(公告)号:US20110193212A1
公开(公告)日:2011-08-11
申请号:US12701642
申请日:2010-02-08
申请人: Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
发明人: Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
IPC分类号: H01L23/522 , H01L21/768
CPC分类号: H01L23/5286 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05093 , H01L2224/13009 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/14505 , H01L2224/16145 , H01L2224/16146 , H01L2224/17517 , H01L2224/48091 , H01L2224/48227 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values.
摘要翻译: 半导体芯片包括电连接阵列和将半导体芯片中的至少一个电路耦合到电接触阵列的多个通孔。 电触点阵列的电触点中的第一个耦合到N个通孔,并且电触点阵列的电触点中的第二个耦合到M个通孔。 M和N是不同值的正整数。
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公开(公告)号:US20100308435A1
公开(公告)日:2010-12-09
申请号:US12479885
申请日:2009-06-08
申请人: Matthew Michael Nowak , Shiqun Gu
发明人: Matthew Michael Nowak , Shiqun Gu
CPC分类号: H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/642 , H01L28/60 , H01L2223/6616 , H01L2223/6622 , H01L2224/0557 , H01L2224/06181 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2224/05552
摘要: A semiconductor die, having a substrate, includes a through silicon via. The through silicon via includes a decoupling capacitor having a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor. The decoupling capacitor is configured to provide local charge storage for components on the semiconductor die.
摘要翻译: 具有基板的半导体管芯包括硅通孔。 贯通硅通孔包括具有第一同轴导体,第二同轴导体和将第一同轴导体与第二同轴导体分离的同轴电介质的去耦电容器。 去耦电容器被配置为为半导体管芯上的部件提供局部电荷存储。
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10.
公开(公告)号:US08508301B2
公开(公告)日:2013-08-13
申请号:US13294351
申请日:2011-11-11
申请人: Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人: Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号: H03F3/14
CPC分类号: H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要: A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.
摘要翻译: 公开了一种三维片上射频放大器,其包括第一和第二变压器和第一晶体管。 第一变压器包括第一和第二电感耦合电感器。 第二变压器包括第三和第四电感耦合电感器。 每个电感器包括在第一金属层中的多个第一段; 第二金属层中的多个第二段; 第一和第二输入以及耦合第一和第二段的多通孔,以形成第一和第二输入之间的连续路径。 第一电感器的第一输入耦合到放大器输入端; 第二电感器的第一输入耦合到第一晶体管栅极; 第三电感器的第一输入耦合到第一晶体管漏极,第四电感器的第一输入耦合到放大器输出端。 第二电感器输入和第一晶体管源耦合到地。
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