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公开(公告)号：US11201162B2
公开(公告)日：2021-12-14
申请号：US16230048
申请日：2018-12-21
发明人： Lee Wang
IPC分类号： H01L27/00 , H01L27/11558 , H01L27/11526 , G11C16/04 , H01L27/11573
摘要： For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.
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公开(公告)号：US09117518B2
公开(公告)日：2015-08-25
申请号：US13724623
申请日：2012-12-21
发明人： Lee Wang
CPC分类号： G11C16/14 , G11C14/00 , G11C14/0054 , G11C14/0063 , G11C19/28
摘要： Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.
摘要翻译： 公开了非易失性寄存器（NVR）和非易失性移位寄存器（NVSR）器件。 本发明的创新的NVR和NVSR设备可以将非易失性存储器元件中存储的非易失性数据快速加载到其对应的静态存储器元件中，以在数字电路中快速和恒定地引用。 根据本发明，从非易失性存储器到静态存储器的加载过程是直接的过程，而不需要经历访问非易失性存储器的常规过程，从非易失性存储器的感测和加载到数字寄存器中并且移位 注册
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公开(公告)号：US11662980B2
公开(公告)日：2023-05-30
申请号：US16675554
申请日：2019-11-06
发明人： Lee Wang
CPC分类号： G06F7/523 , G06F1/03 , G06F7/50 , G06F7/5057 , G11C8/10
摘要： In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.
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公开(公告)号：US11200029B2
公开(公告)日：2021-12-14
申请号：US16850825
申请日：2020-04-16
发明人： Lee Wang
摘要： The base-2n in-memory adder device mainly comprises Perpetual Digital Perceptron (PDP) in-memory adder with Read Only Memory (ROM) arrays for storing the binary sum codes of the addition table for processing the addition operations of two n-bit binary integer operands. Since the integer numbers can be represented by the binary codes of multiple digits of base-2n integer numbers, the base-2n in-memory adder device can iterate multiple times of the digit-additions to complete the binary code addition for two m-digit base-2n integer operands. Consequently, the base-2n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.
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公开(公告)号：US10148254B2
公开(公告)日：2018-12-04
申请号：US15405747
申请日：2017-01-13
发明人： Lee Wang
IPC分类号： G11C5/14 , H03K3/012 , H03K3/356 , G11C11/412 , G11C11/417 , G11C11/419
摘要： The standby leakage current reduction schemes for digital data storing components are disclosed. By floating the low digital voltage node of the digital data storing components in standby mode, the major standby leakage current paths to the ground voltage caused by the channel diffusion leakage current of MOSFET devices can be terminated. The standby leakage currents will be reduced to the small reverse junction leakage currents to the grounded substrate. For retaining the stored data in the digital data storing components in standby mode, the low digital voltage node is connected to the ground voltage periodically according to a plurality of rectangular voltage pulses outputted from a pulse generator trigged by a low frequency clock oscillator. Due to no external voltage bias to the low digital voltage node other than floating the digital low voltage node, the data recovering process is instant.
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公开(公告)号：US09754668B1
公开(公告)日：2017-09-05
申请号：US15059733
申请日：2016-03-03
发明人： Lee Wang
IPC分类号： G11C15/04 , G11C7/22 , G11C5/06 , G06F12/1027 , G06F12/10 , G11C15/00 , G06F12/1036
CPC分类号： G11C7/22 , G06F12/10 , G06F12/1027 , G06F12/1036 , G11C11/005 , G11C11/54 , G11C13/0002 , G11C15/00 , G11C15/04 , G11C15/046
摘要： In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.
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公开(公告)号：US09595330B2
公开(公告)日：2017-03-14
申请号：US15283802
申请日：2016-10-03
发明人： Lee Wang
IPC分类号： G11C15/04
CPC分类号： G11C15/046
摘要： A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.
摘要翻译： 公开了一种由一对互补非易失性存储器件和MOSFET（金属氧化物半导体场效应晶体管）组成的可配置非易失性内容可寻址存储器（CNVCAM）单元。 可以构造CNVCAM单元以形成NOR型匹配线存储器阵列和NAND型匹配线存储器阵列。 与通过存储器位置的先前知识的地址码访问的随机存取存储器（RAM）相反，CNVCAM可以被预先配置成非易失性存储器内容数据，并通过输入内容数据进行搜索以触发进一步的计算过程。 CNVCAM的独特属性可以为神经计算提供关键组件。
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8.发明授权Ultra-low power programming method for N-channel semiconductor non-volatile memory 有权用于N沟道半导体非易失性存储器的超低功耗编程方法公开(公告)号：US09082490B2
公开(公告)日：2015-07-14
申请号：US13920886
申请日：2013-06-18
发明人： Lee Wang
CPC分类号： G11C16/10 , G11C16/0466
摘要： An Ultra-low power programming method for N-channel semiconductor Non-Volatile Memory (NVM) is disclosed. In contrast to the grounded voltage at the source electrode of an N-channel semiconductor NVM for the conventional Channel Hot Electron Injection (CHEI) programming, the source electrode in the programming method of the invention is necessarily floating with no voltage bias to prevent applied electrical fields toward the source electrode. The drain electrode of the N-channel semiconductor NVM is reversely biased with a positive voltage VDB relative to the substrate to facilitate the valence band electrons in the P-type substrate to tunnel to the conducting band of the N-type drain electrode. A positive high gate voltage pulse is then applied to the gate electrode of the N-channel semiconductor NVM to collect the surface energetic electrons toward the charge storage material.
摘要翻译： 公开了一种用于N沟道半导体非易失性存储器（NVM）的超低功率编程方法。 与用于常规通道热电子注入（CHEI）编程的N沟道半导体NVM的源极处的接地电压相反，本发明的编程方法中的源电极必然浮动，没有电压偏置以防止施加的电 场向源电极。 N沟道半导体NVM的漏电极相对于衬底以正电压VDB反向偏置，以便于P型衬底中的价带电子隧穿至N型漏电极的导带。 然后将正高栅极电压脉冲施加到N沟道半导体NVM的栅电极，以将表面能量电子收集到电荷存储材料。
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公开(公告)号：US08988104B2
公开(公告)日：2015-03-24
申请号：US13778784
申请日：2013-02-27
发明人： Lee Wang
IPC分类号： H03K19/173 , G11C11/34
CPC分类号： H03K19/173
摘要： Innovative Non-Volatile Look-Up-Table (NV-LUT) has been constructed by Single Gate Logic Non-Volatile Memory (SGLNVM) devices processed with the standard CMOS logic process. One of a pair of complementary SGLNVM devices is always programmed to the high threshold voltage state and the other remains in the low threshold voltage state. By applying digital voltage rail (VDD and VSS) to the input nodes of the pair of complementary SGLNVM devices, the output node of the pair of complementary SGLNVM devices outputs digital signals according to its configuration. The NV-LUT outputs digital signals from a plurality of pairs of complementary SGLNVM devices through a digital switching multiplexer. The NV-LUT is a good substitution for SRAM based LUT commonly used in Field Programmable Gate Array (FPGA).
摘要翻译： 创新的非易失性查找表（NV-LUT）已经由采用标准CMOS逻辑过程处理的单门逻辑非易失性存储器（SGLNVM）器件构成。 一对互补的SGLNVM器件之一总是被编程为高阈值电压状态，另一个保持在低阈值电压状态。 通过将数字电压轨（VDD和VSS）施加到该对互补SGLNVM器件的输入节点，该对互补SGLNVM器件的输出节点根据其配置输出数字信号。 NV-LUT通过数字开关多路复用器输出来自多对互补SGLNVM器件的数字信号。 NV-LUT是现场可编程门阵列（FPGA）中常用的基于SRAM的LUT的良好替代品。
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公开(公告)号：US11825652B2
公开(公告)日：2023-11-21
申请号：US17514401
申请日：2021-10-29
发明人： Lee Wang
IPC分类号： H01L29/423 , H10B41/60 , G11C16/04 , H10B41/40 , H10B43/40
CPC分类号： H10B41/60 , G11C16/0441 , G11C16/0466 , H10B41/40 , H10B43/40
摘要： For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.
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