公开(公告)号：US4924111A

公开(公告)日：1990-05-08

申请号：US263746

申请日：1988-10-31

申请人： Floyd E. Anderson ,  Stephen P. Robb

发明人： Floyd E. Anderson ,  Stephen P. Robb

IPC分类号： H01L27/02 ,  H03K17/14

CPC分类号： H03K17/145 ,  H01L27/0211 ,  Y10S257/92

摘要： An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

摘要翻译： 描述了具有与大功率晶体管连接的微处理器核心的集成电路。 该集成电路提供智能控制和驱动需要电流超过250毫安的负载的能力。 大功率晶体管内置于与微处理器核心技术相兼容的技术，从而形成更容易制造的电路。 微处理器内核以最热敏微处理器核心电路和功率器件之间提供最大距离的方式布置。 提供片上温度检测和反馈，用于结温监测和控制。

公开(公告)号：US4924112A

公开(公告)日：1990-05-08

申请号：US264732

申请日：1988-10-31

申请人： Floyd E. Anderson ,  Stephen P. Robb ,  Pern Shaw

发明人： Floyd E. Anderson ,  Stephen P. Robb ,  Pern Shaw

IPC分类号： H03K17/08 ,  H03K17/082

CPC分类号： H03K17/0826 ,  H03K17/0822 ,  H03K2017/0806

摘要： An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

摘要翻译： 描述了具有与大功率晶体管连接的微处理器核心的集成电路。 该集成电路提供智能控制和驱动需要电流超过250毫安的负载的能力。 大功率晶体管内置于与微处理器核心技术相兼容的技术，从而形成更容易制造的电路。 微处理器内核以最热敏微处理器核心电路和功率器件之间提供最大距离的方式布置。 提供片上温度检测和反馈，用于结温监测和控制。

公开(公告)号：US4918333A

公开(公告)日：1990-04-17

申请号：US264733

申请日：1988-10-31

申请人： Floyd E. Anderson ,  Stephen P. Robb ,  Pern Shaw ,  Lewis E. Terry

发明人： Floyd E. Anderson ,  Stephen P. Robb ,  Pern Shaw ,  Lewis E. Terry

IPC分类号： G06F15/78 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H03K17/06

CPC分类号： H01L27/0207 ,  H03K17/063 ,  H01L27/0203

摘要： An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

公开(公告)号：US4700124A

公开(公告)日：1987-10-13

申请号：US944107

申请日：1986-12-22

申请人： Floyd E. Anderson

发明人： Floyd E. Anderson

IPC分类号： G05F1/613

CPC分类号： G05F1/613

摘要： A voltage regulator circuit which provides a regulated output voltage by regulating output current at an output terminal is provided. The voltage regulator circuit operates in response to a clocked control signal. The regulated output voltage and a delayed signal of the regulated output voltage are both used to bias a selected one of series-connected transistors which sink current from the output terminal in response to the value of the output voltage and the frequency of the clocked control signal. A second control signal is provided for enabling or disabling the voltage regulator circuit.

摘要翻译： 提供了通过调节输出端子处的输出电流来提供调节输出电压的电压调节器电路。 电压调节器电路响应时钟控制信号而工作。 调节输出电压和稳压输出电压的延迟信号都用于偏置所选择的一个串联连接的晶体管，其响应于输出电压的值和时钟控制信号的频率从输出端吸收电流 。 提供第二控制信号用于启用或禁用稳压器电路。

公开(公告)号：US4851892A

公开(公告)日：1989-07-25

申请号：US94246

申请日：1987-09-08

申请人： Floyd E. Anderson ,  Richard R. Hamzik

发明人： Floyd E. Anderson ,  Richard R. Hamzik

IPC分类号： H01L21/765 ,  H01L27/118

CPC分类号： H01L27/11807 ,  H01L21/765

摘要： A standard cell array is disclosed having improved device isolation, customized metal routing under power busses, a gate array core cell having improved internal routing channels, and shared power busses. A fake gate is located adjacent a source of drain of a transistor within each cell, and is coupled to a supply voltage for isolating the transistors within each cell. Additional metallization strips partially overlap and extend between adjacent rows and columns, respectively, of the core cells for providing supply voltages thereto. Further metallization strips for conducting signals overlie the internal portion of the core cell and extend the entire length of the row or column of core cells.

摘要翻译： 公开了一种标准单元阵列，其具有改进的器件隔离，功率总线下的定制金属布线，具有改进的内部布线通道的门阵列核心单元和共享功率总线。 假栅极位于每个单元内的晶体管的漏极源附近，并且耦合到用于隔离每个单元中的晶体管的电源电压。 另外的金属化条分别在芯单元的相邻行和列之间部分地重叠并延伸，以便向其提供电源电压。 用于传导信号的另外的金属化条覆盖在核心单元的内部部分并延伸核心单元的行或列的整个长度。

公开(公告)号：US4635261A

公开(公告)日：1987-01-06

申请号：US748885

申请日：1985-06-26

申请人： Floyd E. Anderson ,  Liang-Tsai Lin

发明人： Floyd E. Anderson ,  Liang-Tsai Lin

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H03K19/00

CPC分类号： G01R31/318536 ,  G01R31/2884 ,  G01R31/318516

摘要： An on chip test system for arrays is provided that includes self test and maintenance operation while allowing for both synchronous and pipeline modes of normal operation. The system is integrated on a chip that includes a plurality of inputs and a plurality of outputs. A plurality of gates are coupled between the plurality of inputs and outputs wherein input signals may be transmitted asynchronously to the gates and output signals may be transmitted asynchronously to the outputs. An input shift register is coupled between each of the inputs and the gates for synchronously transmitting input signals, and an output shift register is coupled between the gates and each of the outputs for synchronously transmitting output signals. A control logic circuit is coupled to the plurality of gates, the input shift registers, and the output shift registers for selecting the systems mode of operation. A comparator circuit is coupled to the output shift registers for comparing said output signals with expected signals.

摘要翻译： 提供了阵列的片上测试系统，包括自检和维护操作，同时允许正常操作的同步和流水线模式。 该系统集成在包括多个输入和多个输出的芯片上。 多个门耦合在多个输入和输出之间，其中输入信号可以异步地发送到门，并且输出信号可以异步发送到输出。 输入移位寄存器耦合在每个输入端和栅极之间，用于同步传输输入信号，输出移位寄存器耦合在栅极和每个输出端之间，用于同步传输输出信号。 控制逻辑电路耦合到多个门，输入移位寄存器和用于选择系统操作模式的输出移位寄存器。 比较器电路耦合到输出移位寄存器，用于将所述输出信号与预期信号进行比较。