公开(公告)号：US06452864B1

公开(公告)日：2002-09-17

申请号：US09774539

申请日：2001-01-31

申请人： Carmelo Condemi ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

发明人： Carmelo Condemi ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/106 ,  G11C7/1069 ,  G11C8/04 ,  G11C8/12 ,  G11C8/18

摘要： An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.

摘要翻译： 交错存储器包括分成第一存储单元组和第二存储单元组的存储器单元阵列。 交错存储器以突发存取模式运行。 第一地址计数器耦合到第一存储单元组，并且地址寄存器耦合到第一地址计数器和第二存储单元组。 定时电路向第一地址计数器产生增量脉冲，使得第一随机存取异步读周期从第一存储单元组开始。 第二存储单元组的地址计数器的功能正在通过将第一地址计数器的内容与地址寄存器进行对应来执行。

公开(公告)号：US06366634B2

公开(公告)日：2002-04-02

申请号：US09774878

申请日：2001-01-31

申请人： Luca Giuseppe De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Promod Kumar ,  Carmelo Condemi

发明人： Luca Giuseppe De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Promod Kumar ,  Carmelo Condemi

IPC分类号： G06M300

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

摘要： An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.

摘要翻译： 用于交织的地址二进制计数器，其具有被划分为第一存储单元组和第二存储单元组的存储器单元的阵列，包括与存储在一行存储单元 银行和进位计算网络。 交织的存储器以启用信号启用的突发存取模式工作。 进位计算网络包括有序组的独立进位发生器。 每个独立进位发生器包括一定数量的级，其中每个级具有从最低有效位开始有序地接收其自身使能位和存储体的一行的连续位数等于级数的输入。 有序组的第一进位发生器的使能位是使能信号，有序组的任何其他进位发生器的使能位是使能信号和先前进位发生器的输入位的逻辑“与” 订购组。

公开(公告)号：US06487140B2

公开(公告)日：2002-11-26

申请号：US09773363

申请日：2001-01-31

申请人： Francesco Tomaiuolo ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

发明人： Francesco Tomaiuolo ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

摘要： A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with an external timing signal, an output register for storing data available at an output of the system, and a selection multiplexer for transferring the data from the plurality of data sources to the output register. The control circuit includes a plurality of circuit blocks, with each circuit block being dedicated to one of the plurality of data sources. Each circuit block includes a detection circuit for detecting availability of the data at an output of a selected data source, and a conditioned update path connected to the detection circuit provides an update flag. A logic gate having a first input receives the update flag and a second input receives an output signal from the detection circuit for providing a selection signal for the selection multiplexer.

摘要翻译： 控制电路管理诸如交错存储器之类的系统内的数据的传送。 该系统包括用于提供与外部定时信号同步的输出数据流的多个数据源，用于存储在系统的输出端可用的数据的输出寄存器，以及用于将数据从多个数据源传送到 输出寄存器。 控制电路包括多个电路块，每个电路块专用于多个数据源之一。 每个电路块包括检测电路，用于检测所选择的数据源的输出端的数据的可用性，并且连接到检测电路的条件更新路径提供更新标志。 具有第一输入的逻辑门接收更新标志，第二输入接收来自检测电路的输出信号，为选择多路复用器提供选择信号。

公开(公告)号：US06624679B2

公开(公告)日：2003-09-23

申请号：US09773269

申请日：2001-01-31

申请人： Francesco Tomaiuolo ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

发明人： Francesco Tomaiuolo ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC分类号： H03H1126

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

摘要： A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.

公开(公告)号：US06470431B2

公开(公告)日：2002-10-22

申请号：US09774542

申请日：2001-01-31

申请人： Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

发明人： Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC分类号： C06F1200

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

摘要： An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

摘要翻译： 具有交错数据路径的交错存储器包括分成第一存储单元组和第二存储单元组的存储器单元的阵列，分别耦合到第一和第二存储单元组的读出放大器的第一和第二阵列，以及 分别耦合到第一和第二读出放大器阵列的第一和第二读取寄存器。 控制和定时电路连接到第一和第二读出放大器阵列，并且具有用于接收外部产生的命令信号的输入，以及用于提供路径选择信号和控制信号的输出。 第三寄存器连接到第一和第二读取寄存器，并且具有用于根据路径选择信号接收其中的读取数据的输入。 一个通道阵列连接到第三寄存器，并被控制信号共同控制，以便将存储在第三寄存器中的读取数据传送到输出缓冲器阵列。

公开(公告)号：US06625706B2

公开(公告)日：2003-09-23

申请号：US09773760

申请日：2001-01-31

申请人： Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

发明人： Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

摘要： A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for the address counters of the memory cell array. Following each increment pulse, a dummy ATD pulse is generated. The dummy ATD pulse is undistinguishable from an ATD pulse generated upon detection of a switching of external address lines.

摘要翻译： 当以顺序访问的同步模式读取存储器中的数据时，顺序读取周期的开始同步的方法使用增量脉冲作为存储器单元阵列的地址计数器的同步信号。 在每个增量脉冲之后，产生伪ATD脉冲。 虚拟ATD脉冲与检测到外部地址线的切换时产生的ATD脉冲无法区分。

公开(公告)号：US06587913B2

公开(公告)日：2003-07-01

申请号：US09773300

申请日：2001-01-31

申请人： Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar ,  Luigi Pascucci

发明人： Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Promod Kumar ,  Luigi Pascucci

IPC分类号： G06F1200

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

摘要： A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.

摘要翻译： 适用于更广泛应用的多用途存储器件，无论是要求以随机存取（如在标准存储器中）或具有顺序或突发型访问的同步顺序模式的异步模式中的数据读取，都能够识别 访问模式和微处理器当前需要的读取模式。 存储器设备将其内部电路作为这种识别的功能进行自我调整，以便以所请求的模式读取数据，而不需要使用额外的外部控制信号和/或暗示相对于访问时间和读取时间的惩罚 对于相同的制造技术和现有技术设计的那些，可以通过专门为一种或另一种操作模式设计的存储器件来实现。

公开(公告)号：US06473339B2

公开(公告)日：2002-10-29

申请号：US09773272

申请日：2001-01-31

申请人： Luca Giuseppe De Ambroggi ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Promod Kumar

发明人： Luca Giuseppe De Ambroggi ,  Fabrizio Campanale ,  Salvatore Nicosia ,  Francesco Tomaiuolo ,  Promod Kumar

IPC分类号： G11C700

CPC分类号： G11C29/78

摘要： A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.

摘要翻译： 用于存储器的冗余架构包括被分成至少一对可单独寻址的半阵列的存储器单元的阵列。 每个半阵列组织成行和列。 冗余架构包括多个包括冗余列的分组。 分组被分成两个分组子集。 每个分组可以通过相应的地址电路独立于另一个分组。 每个数据包还提供专用于相应半数组的冗余列。

公开(公告)号：US06356505B2

公开(公告)日：2002-03-12

申请号：US09773283

申请日：2001-01-31

申请人： Salvatore Nicosia ,  Fabrizio Campanale ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Luigi Pascucci

发明人： Salvatore Nicosia ,  Fabrizio Campanale ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Luigi Pascucci

IPC分类号： G11C818

CPC分类号： G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

摘要： An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.

摘要翻译： 基于外部产生的包括地址锁存使能信号和芯片使能信号的命令信号，交错存储器在顺序存取同步模式和随机存取异步模式下是可读的。 存储器包括用于再生外部产生的地址锁存使能信号的电路。 第一和第二内部复制信号由电路产生。 第二内部复制信号具有相对于第一内部副本信号的前沿被延迟的前沿。 第二内部副本信号的持续时间有条件地增加，以防止当交错存储器以顺序存取同步模式或随机存取异步模式运行时外部产生的地址锁存使能信号和外部产生的芯片使能信号之间的不同步 。

公开(公告)号：US07389384B2

公开(公告)日：2008-06-17

申请号：US10512620

申请日：2003-04-22

申请人： Gijs Van Steenwijk ,  Fabrizio Campanale

发明人： Gijs Van Steenwijk ,  Fabrizio Campanale

IPC分类号： G06F12/06

CPC分类号： G06F9/3802 ,  G06F12/0246 ,  G06F12/0802

摘要： The integrated circuit according to the invention comprises a processor (603), a non-volatile memory (602) and an interface (605), where said interface (605) contains a first cache memory (601.1) and a second cache memory (601.2) and connects the processor (603) to the non-volatile memory (602). The interface (605) gets data from the non-volatile memory (602) and stores them in said first or said second cache memory (601.1, 601.2) intermediately and provides the processor (603) with data from said first cache memory (601.1) or from said second cache memory (601.2), depending on where the requested data are stored.

摘要翻译： 根据本发明的集成电路包括处理器（603），非易失性存储器（602）和接口（605），其中所述接口（605）包含第一高速缓存存储器（601.1）和第二高速缓冲存储器（601.2） ）并将处理器（603）连接到非易失性存储器（602）。 接口（605）从非易失性存储器（602）获取数据并将其存储在所述第一或所述第二高速缓存存储器（601.1,601.2）中，并且向处理器（603）提供来自所述第一高速缓冲存储器（601.1）的数据， 或从所述第二高速缓存存储器（601.2）中取决于所请求的数据的存储位置。