-
1.发明申请Method for fetching data from a non-volatile memory in an integrated circuit and corresponding integrated circuit 失效用于从集成电路中的非易失性存储器和相应的集成电路获取数据的方法公开(公告)号：US20050166004A1
公开(公告)日：2005-07-28
申请号：US10512621
申请日：2003-04-29
CPC分类号： G06F12/0802 , G06F2212/2022
摘要： The method uses an integrated circuit comprising a processor (603), a non-volatile memory (602), especially a flash memory, a system clock and an interface (605), which is connected on the one side to the (processor (602) and on the other side to the non-volatile memory (602). When the address (ba[ ]) provided by the processor (603) has changed, the interface (605) leads the address (ba[ ]) to the non-volatile memory (602), creates a strobe signal (CL; DCR) within the system clock cycle during which the address (ba[ ]) has changed and directs it to the non-volatile memory (602). As soon as the data in the non-volatile memory (602) corresponding to the address (ba[ ]) are available the data will be directed to the processor (603). Thereby it is possible to get on the integrated circuit the highest data throughput according to the flash memory (602) access time and a minimized chip area at the same time.
摘要翻译： 该方法使用包括处理器（603），非易失性存储器（602），特别是闪存，系统时钟和接口（605）的集成电路，其在一侧连接到（处理器（602） ）并且在另一侧到非易失性存储器（602），当由处理器（603）提供的地址（ba []）改变时，接口（605）将地址（ba []）引导到非易失性存储器 非易失性存储器（602）在地址（ba []）已经改变的系统时钟周期内产生选通信号（CL; DCR），并将其引导到非易失性存储器（602）。 在对应于地址（ba []）的非易失性存储器（602）中，数据将被引导到处理器（603），从而可以根据闪存将集成电路的数据吞吐量提高到最高 存储器（602）访问时间和最小化的芯片区域。
-
公开(公告)号：US07389384B2
公开(公告)日：2008-06-17
申请号：US10512620
申请日：2003-04-22
IPC分类号： G06F12/06
CPC分类号： G06F9/3802 , G06F12/0246 , G06F12/0802
摘要： The integrated circuit according to the invention comprises a processor (603), a non-volatile memory (602) and an interface (605), where said interface (605) contains a first cache memory (601.1) and a second cache memory (601.2) and connects the processor (603) to the non-volatile memory (602). The interface (605) gets data from the non-volatile memory (602) and stores them in said first or said second cache memory (601.1, 601.2) intermediately and provides the processor (603) with data from said first cache memory (601.1) or from said second cache memory (601.2), depending on where the requested data are stored.
摘要翻译： 根据本发明的集成电路包括处理器（603），非易失性存储器（602）和接口（605），其中所述接口（605）包含第一高速缓存存储器（601.1）和第二高速缓冲存储器（601.2） ）并将处理器（603）连接到非易失性存储器（602）。 接口（605）从非易失性存储器（602）获取数据并将其存储在所述第一或所述第二高速缓存存储器（601.1,601.2）中，并且向处理器（603）提供来自所述第一高速缓冲存储器（601.1）的数据， 或从所述第二高速缓存存储器（601.2）中取决于所请求的数据的存储位置。
-
3.发明授权Method for fetching data from a non-volatile memory in an integrated circuit and corresponding integrated circuit 失效用于从集成电路中的非易失性存储器和相应的集成电路获取数据的方法公开(公告)号：US07536509B2
公开(公告)日：2009-05-19
申请号：US10512621
申请日：2003-04-29
CPC分类号： G06F12/0802 , G06F2212/2022
摘要： The method uses an integrated circuit comprising a processor (603), a non-volatile memory (602), especially a flash memory, a system clock and an interface (605), which is connected on the one side to the processor (602) and on the other side to the non-volatile memory (602). When the address (ba[ ]) provided by the processor (603) has changed, the interface (605) leads the address (ba[ ]) to the non-volatile memory (602), creates a strobe signal (CL; DCR) within the system clock cycle during which the address (ba[ ]) has changed and directs it to the non-volatile memory (602). As soon as the data in the non-volatile memory (602) corresponding to the address (ba[ ]) are available the data will be directed to the processor (603). Thereby it is possible to get on the integrated circuit the highest data throughput according to the flash memory (602) access time and a minimized chip area at the same time.
摘要翻译： 该方法使用包括处理器（603），非易失性存储器（602），特别是快闪存储器，系统时钟和接口（605）的集成电路，其在一侧连接到处理器（602） 并且在另一侧到非易失性存储器（602）。 当由处理器（603）提供的地址（ba []）改变时，接口605将地址（ba []）引导到非易失性存储器（602），产生选通信号（CL; DCR） 在地址（ba []）已经改变的系统时钟周期内，并将其引导到非易失性存储器（602）。 一旦对应于地址（ba []）的非易失性存储器（602）中的数据可用，数据将被引导到处理器（603）。 因此，可以根据闪存（602）访问时间和同时最小化的芯片面积，使集成电路达到最高的数据吞吐量。
-
公开(公告)号：US20060004949A1
公开(公告)日：2006-01-05
申请号：US10512620
申请日：2003-04-22
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F12/0246 , G06F12/0802
摘要： The integrated circuit according to the invention comprises a processor (603), a non-volatile memory (602) and an interface (605), where said interface (605) contains a first cache memory (601.1) and a second cache memory (601.2) and connects the processor (603) to the non-volatile memory (602). The interface (605) gets data from the non-volatile memory (602) and stores them in said first or said second cache memory (601.1, 601.2) intermediately and provides the processor (603) with data from said first cache memory (601.1) or from said second cache memory (601.2), depending on where the requested data are stored.
摘要翻译： 根据本发明的集成电路包括处理器（603），非易失性存储器（602）和接口（605），其中所述接口（605）包含第一高速缓存存储器（601.1）和第二高速缓冲存储器（601.2） ）并将处理器（603）连接到非易失性存储器（602）。 接口（605）从非易失性存储器（602）获取数据并将其存储在所述第一或所述第二高速缓存存储器（601.1,601.2）中，并且向处理器（603）提供来自所述第一高速缓冲存储器（601.1）的数据， 或从所述第二高速缓存存储器（601.2）中取决于所请求的数据的存储位置。
-
5.发明授权Interleaved memory device for sequential access synchronous reading with simplified address counters 有权用于顺序访问同步读取的交错存储器件，具有简化的地址计数器公开(公告)号：US06452864B1
公开(公告)日：2002-09-17
申请号：US09774539
申请日：2001-01-31
申请人： Carmelo Condemi , Fabrizio Campanale , Salvatore Nicosia , Francesco Tomaiuolo , Luca Giuseppe De Ambroggi , Promod Kumar
发明人： Carmelo Condemi , Fabrizio Campanale , Salvatore Nicosia , Francesco Tomaiuolo , Luca Giuseppe De Ambroggi , Promod Kumar
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1018 , G11C7/1039 , G11C7/1042 , G11C7/106 , G11C7/1069 , G11C8/04 , G11C8/12 , G11C8/18
摘要： An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.
摘要翻译： 交错存储器包括分成第一存储单元组和第二存储单元组的存储器单元阵列。 交错存储器以突发存取模式运行。 第一地址计数器耦合到第一存储单元组，并且地址寄存器耦合到第一地址计数器和第二存储单元组。 定时电路向第一地址计数器产生增量脉冲，使得第一随机存取异步读周期从第一存储单元组开始。 第二存储单元组的地址计数器的功能正在通过将第一地址计数器的内容与地址寄存器进行对应来执行。
-
公开(公告)号：US06366634B2
公开(公告)日：2002-04-02
申请号：US09774878
申请日：2001-01-31
申请人： Luca Giuseppe De Ambroggi , Salvatore Nicosia , Francesco Tomaiuolo , Fabrizio Campanale , Promod Kumar , Carmelo Condemi
发明人： Luca Giuseppe De Ambroggi , Salvatore Nicosia , Francesco Tomaiuolo , Fabrizio Campanale , Promod Kumar , Carmelo Condemi
IPC分类号： G06M300
CPC分类号： G11C7/1057 , G11C7/1018 , G11C7/1039 , G11C7/1042 , G11C7/1045 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C8/04 , G11C8/18
摘要： An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.
摘要翻译： 用于交织的地址二进制计数器，其具有被划分为第一存储单元组和第二存储单元组的存储器单元的阵列，包括与存储在一行存储单元 银行和进位计算网络。 交织的存储器以启用信号启用的突发存取模式工作。 进位计算网络包括有序组的独立进位发生器。 每个独立进位发生器包括一定数量的级，其中每个级具有从最低有效位开始有序地接收其自身使能位和存储体的一行的连续位数等于级数的输入。 有序组的第一进位发生器的使能位是使能信号，有序组的任何其他进位发生器的使能位是使能信号和先前进位发生器的输入位的逻辑“与” 订购组。
-
7.发明授权Circuit for managing the transfer of data streams from a plurality of sources within a system 有权用于管理从系统内的多个源传输数据流的电路公开(公告)号：US06487140B2
公开(公告)日：2002-11-26
申请号：US09773363
申请日：2001-01-31
申请人： Francesco Tomaiuolo , Fabrizio Campanale , Salvatore Nicosia , Luca Giuseppe De Ambroggi , Promod Kumar
发明人： Francesco Tomaiuolo , Fabrizio Campanale , Salvatore Nicosia , Luca Giuseppe De Ambroggi , Promod Kumar
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1018 , G11C7/1039 , G11C7/1042 , G11C7/1045 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C8/04 , G11C8/18
摘要： A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with an external timing signal, an output register for storing data available at an output of the system, and a selection multiplexer for transferring the data from the plurality of data sources to the output register. The control circuit includes a plurality of circuit blocks, with each circuit block being dedicated to one of the plurality of data sources. Each circuit block includes a detection circuit for detecting availability of the data at an output of a selected data source, and a conditioned update path connected to the detection circuit provides an update flag. A logic gate having a first input receives the update flag and a second input receives an output signal from the detection circuit for providing a selection signal for the selection multiplexer.
摘要翻译： 控制电路管理诸如交错存储器之类的系统内的数据的传送。 该系统包括用于提供与外部定时信号同步的输出数据流的多个数据源，用于存储在系统的输出端可用的数据的输出寄存器，以及用于将数据从多个数据源传送到 输出寄存器。 控制电路包括多个电路块，每个电路块专用于多个数据源之一。 每个电路块包括检测电路，用于检测所选择的数据源的输出端的数据的可用性，并且连接到检测电路的条件更新路径提供更新标志。 具有第一输入的逻辑门接收更新标志，第二输入接收来自检测电路的输出信号，为选择多路复用器提供选择信号。
-
8.发明申请Method for writing data to a non-volatile memory embedded in an integrated circuit and corresponding circuit 审中-公开将数据写入嵌入在集成电路中的非易失性存储器和相应电路的方法公开(公告)号：US20050268157A1
公开(公告)日：2005-12-01
申请号：US10516643
申请日：2003-06-04
申请人： Fabrizio Campanale
发明人： Fabrizio Campanale
CPC分类号： G06F9/3802 , G06F8/65 , G06F9/24 , G06F9/3824
摘要： The invention is a method and a circuit for writing data (DATA) from a processor (603) to a non-volatile memory (602) embedded in an integrated circuit. The main objective is to optimize the use of this embedded non-volatile memory. The method comprises a number of steps: The data to be written to the non-volatile memory (602) is first transferred to a volatile memory (601). Thereafter, a wait signal (wait) will be send to the processor (603). Then, the data (DATA) will be transferred from the volatile memory (601) to the non-volatile memory (602). At last, the wait signal (wait) will be removed. Thus the non-volatile memory (602) can be used both as instruction memory and as RAM, which achieves the main goal of this invention. The corresponding circuitry is a complex integrated circuit equipped to execute the above functions.
摘要翻译： 本发明是一种用于将数据（DATA）从处理器（603）写入嵌入集成电路中的非易失性存储器（602）的方法和电路。 主要目标是优化这种嵌入式非易失性存储器的使用。 该方法包括多个步骤：要写入非易失性存储器（602）的数据首先被传送到易失性存储器（601）。 此后，等待信号（等待）将发送到处理器（603）。 然后，数据（DATA）将从易失性存储器（601）传送到非易失性存储器（602）。 最后，等待信号（等待）将被删除。 因此，非易失性存储器（602）可以用作指令存储器和RAM，这实现了本发明的主要目标。 相应的电路是配备执行上述功能的复杂集成电路。
-
9.发明授权Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data 有权用于交错存储器和负载脉冲发生器电路的交错数据路径和输出管理架构，用于输出读取的数据公开(公告)号：US06470431B2
公开(公告)日：2002-10-22
申请号：US09774542
申请日：2001-01-31
申请人： Salvatore Nicosia , Francesco Tomaiuolo , Fabrizio Campanale , Luca Giuseppe De Ambroggi , Promod Kumar
发明人： Salvatore Nicosia , Francesco Tomaiuolo , Fabrizio Campanale , Luca Giuseppe De Ambroggi , Promod Kumar
IPC分类号： C06F1200
CPC分类号： G11C7/1057 , G11C7/1018 , G11C7/1039 , G11C7/1042 , G11C7/1045 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C8/04 , G11C8/18
摘要： An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.
摘要翻译： 具有交错数据路径的交错存储器包括分成第一存储单元组和第二存储单元组的存储器单元的阵列，分别耦合到第一和第二存储单元组的读出放大器的第一和第二阵列，以及 分别耦合到第一和第二读出放大器阵列的第一和第二读取寄存器。 控制和定时电路连接到第一和第二读出放大器阵列，并且具有用于接收外部产生的命令信号的输入，以及用于提供路径选择信号和控制信号的输出。 第三寄存器连接到第一和第二读取寄存器，并且具有用于根据路径选择信号接收其中的读取数据的输入。 一个通道阵列连接到第三寄存器，并被控制信号共同控制，以便将存储在第三寄存器中的读取数据传送到输出缓冲器阵列。
-
公开(公告)号：US06624679B2
公开(公告)日：2003-09-23
申请号：US09773269
申请日：2001-01-31
申请人： Francesco Tomaiuolo , Fabrizio Campanale , Salvatore Nicosia , Luca Giuseppe De Ambroggi , Promod Kumar
发明人： Francesco Tomaiuolo , Fabrizio Campanale , Salvatore Nicosia , Luca Giuseppe De Ambroggi , Promod Kumar
IPC分类号： H03H1126
CPC分类号： G11C7/1057 , G11C7/1018 , G11C7/1039 , G11C7/1042 , G11C7/1045 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C8/04 , G11C8/18
摘要： A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.014 秒)
