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    Mechanism for enforcing the correct order of instruction execution
    1.
    发明授权
    Mechanism for enforcing the correct order of instruction execution 失效
    执行指令执行顺序的机制

    公开(公告)号：US5420990A

    公开(公告)日：1995-05-30

    申请号：US79494

    申请日：1993-06-17

    申请人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowney

    发明人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowney

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3834 ,  G06F9/3842

    摘要： An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.

    摘要翻译： 用于执行所选指令的装置以正确的顺序执行，包括用于存储由所选择的指令从存储器读取的数据的加载地址的第一内容可寻址存储器。 第一内容可寻址存储器将存储地址与要写入存储器的数据的加载地址进行比较。 所述第一内容可寻址存储器产生第一信号，如果所述加载地址之一与随后比较的一个所述存储地址相同。 该装置还包括第二内容可寻址存储器，用于存储和比较由所选指令读和写的数据的状态。 如果存储状态之一与所述比较状态之一相同，则第二内容可寻址存储器产生第二信号。 所存储的状态包括在检测到第一和第二信号时重复所选指令的执行的程序计数器。

    Mechanism for executing computer instructions in parallel
    3.
    发明授权
    Mechanism for executing computer instructions in parallel 失效
    并行执行计算机指令的机制

    公开(公告)号：US06704861B1

    公开(公告)日：2004-03-09

    申请号：US08752729

    申请日：1996-11-19

    申请人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowney

    发明人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowney

    IPC分类号： G06F938

    CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/3865

    摘要： A mechanism for executing computer instructions in parallel includes a compiler for generating and grouping instructions into a plurality of sets of instructions to be executed in parallel, each set having a unique identification. A computer system having a real state and a speculative state executes the sets in parallel, the computer system executing a particular set of instructions in the speculative state if the instructions of the particular set have dependencies which can not be resolved until the instructions are actually executed. The computer system generates speculative data while executing instructions in the speculative state. Logic circuits are provided to detect any exception conditions which occur while executing the particular set in the speculative state. If the particular set is subject to an exception condition, the instructions of the set are re-executed to resolve the exception condition, and to incorporate the speculative data in the real state of the computer system.

    摘要翻译： 用于并行执行计算机指令的机构包括：编译器，用于将指令生成和分组成并行执行的多组指令，每组具有唯一的标识。 具有实际状态和推测状态的计算机系统并行地执行集合，如果特定集合的指令具有在实际执行指令之前无法解析的依赖关系，则计算机系统在推测状态下执行特定指令集 。 计算机系统在推测状态下执行指令时生成推测数据。 提供逻辑电路以检测在推测状态下执行特定集合时发生的任何异常情况。 如果特定集合受到异常条件的影响，则重新执行该集合的指令以解决异常条件，并将推测数据并入计算机系统的实际状态。

    Method and apparatus for propagating exception conditions of a computer system
    4.
    发明授权
    Method and apparatus for propagating exception conditions of a computer system 失效
    传播计算机系统异常情况的方法和装置

    公开(公告)号：US5428807A

    公开(公告)日：1995-06-27

    申请号：US79498

    申请日：1993-06-17

    申请人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowny

    发明人： Francis X. McKeen ,  Michael C. Adler ,  Joel S. Emer ,  Robert P. Nix ,  David J. Sager ,  P. Geoffrey Lowny

    IPC分类号： G06F9/38 ,  G06F9/00

    CPC分类号： G06F9/3865 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3863

    摘要： There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.

    摘要翻译： 当指令受到异常条件的限制时，提供了一种在计算机系统中传播异常情况的机制。 该装置包括一组数据寄存器，用于存储由计算机系统的指令操纵的数据，以及一组状态寄存器，用于存储由指令操纵的数据的推测状态，存在与每个数据寄存器相关联的一个状态寄存器。 此外，该装置包括耦合到一组状态寄存器的逻辑电路，用于将状态从状态寄存器中的一个状态寄存器传播到状态寄存器的目的地寄存器，如果数据存储在相关源中的一个数据寄存器 被用作相关联的目的地数据寄存器的源，并且如果存储在源数据寄存器中的数据被受异常条件的特定指令操纵。

    Breaking replay dependency loops in a processor using a rescheduled replay queue
    5.
    发明授权
    Breaking replay dependency loops in a processor using a rescheduled replay queue 失效
    使用重新安排的重播队列在处理器中重新播放依赖循环

    公开(公告)号：US06981129B1

    公开(公告)日：2005-12-27

    申请号：US09705668

    申请日：2000-11-02

    申请人： Darrell D. Boggs ,  Douglas M. Carmean ,  Per H. Hammarlund ,  Francis X. McKeen ,  David J. Sager ,  Ronak Singhal

    发明人： Darrell D. Boggs ,  Douglas M. Carmean ,  Per H. Hammarlund ,  Francis X. McKeen ,  David J. Sager ,  Ronak Singhal

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3842 ,  G06F9/3861

    摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

    摘要翻译： 使用重新安排的重播队列在处理器中重新播放依赖循环。 所述处理器包括用于接收多个指令的重放队列，以及执行所述多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。 当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。 检查器耦合到执行单元以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

    TRACKING CONTROL FLOW OF INSTRUCTIONS
    7.
    发明申请
    TRACKING CONTROL FLOW OF INSTRUCTIONS 有权
    跟踪指令的控制流程

    公开(公告)号：US20140281424A1

    公开(公告)日：2014-09-18

    申请号：US13834049

    申请日：2013-03-15

    申请人： Jayaram Bobba ,  Ruchira Sasanka ,  Jeffrey J. Cook ,  Abhinav Das ,  Arvind Krishnaswamy ,  David J. Sager ,  Jason M. Agron

    发明人： Jayaram Bobba ,  Ruchira Sasanka ,  Jeffrey J. Cook ,  Abhinav Das ,  Arvind Krishnaswamy ,  David J. Sager ,  Jason M. Agron

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3005 ,  G06F8/433 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/076 ,  G06F11/3466

    摘要： A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.

    摘要翻译： 公开了一种用于跟踪应用程序中的指令的控制流程并基于应用程序中的指令的控制流程执行处理设备的一个或多个优化的机制。 生成控制流数据以指示应用程序中的指令块的控制流程。 控制流数据可以包括指示是否可以针对不同的指令块执行优化的注释。 控制流数据还可以用于跟踪指令的执行以确定指令块中的指令是否被分配给处理器的线程，进程和/或执行核心，并且确定错误是否具有 在执行指令期间发生。

    MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS
    9.
    发明申请
    MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS 审中-公开
    用于SMT订单处理器的免费物理寄存器识别器的机制

    公开(公告)号：US20090327661A1

    公开(公告)日：2009-12-31

    申请号：US12165186

    申请日：2008-06-30

    申请人： Zeev Sperber ,  David J. Sager ,  Fernando Latorre ,  Ori Lempel ,  Evgeni Krimer ,  Bishara Shomar

    发明人： Zeev Sperber ,  David J. Sager ,  Fernando Latorre ,  Ori Lempel ,  Evgeni Krimer ,  Bishara Shomar

    IPC分类号： G06F9/305

    CPC分类号： G06F9/3851 ,  G06F9/30098 ,  G06F9/384 ,  G06F9/3885

    摘要： Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers corresponding to the plurality of registers. An instruction may read the architectural data from the physical register file at dispatch. Other embodiments are also described and claimed.

    摘要翻译： 描述了用于处理SMT（同时多线程）无序处理器的免费物理寄存器标识符的机制的方法和装置。 在一些实施例中，物理寄存器文件存储对应于多个寄存器的推测数据和架构数据。 空闲列表逻辑可以保持与多个寄存器对应的空闲物理寄存器标识符。 指令可以在调度时从物理寄存器文件读取架构数据。 还描述和要求保护其他实施例。

    Multi-threading techniques for a processor utilizing a replay queue
    10.
    发明授权
    Multi-threading techniques for a processor utilizing a replay queue 有权
    使用重放队列的处理器的多线程技术

    公开(公告)号：US07219349B2

    公开(公告)日：2007-05-15

    申请号：US10792154

    申请日：2004-03-02

    申请人： Amit A. Merchant ,  Darrell D. Boggs ,  David J. Sager

    发明人： Amit A. Merchant ,  Darrell D. Boggs ,  David J. Sager

    IPC分类号： G06F9/46 ,  G06F9/40 ,  G06F15/76

    CPC分类号： G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3869

    摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

    摘要翻译： 提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。 重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。 在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。 通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。