公开(公告)号：US07010735B2

公开(公告)日：2006-03-07

申请号：US10043486

申请日：2002-01-10

申请人： Franco Motika ,  Philip J. Nigh ,  Peilin Song

发明人： Franco Motika ,  Philip J. Nigh ,  Peilin Song

IPC分类号： G01R31/28

CPC分类号： G11C29/025 ,  G01R31/318342 ,  G11C29/02 ,  G11C29/32

摘要： While data cannot be transmitted down a scan chain through a stuck-at fault location, data in properly operating latches downstream of the stuck-at fault location can be shifted down the chain. By varying operating parameters, such as power supply and reference voltages, clock timing patterns, temperature and timing sequences, one or more latches down the SRL chain from the stuck-at fault location may be triggered to change state from the stuck-at fault value. The SRL chain is then operated to shift data out the output of the SRL chain. The output is monitored and any change in value from the stuck-at state is noted as identifying all good latch positions to end of the chain. The process is repeated: varying each of the selected operating parameters until the latch position following the stuck-at fault latch is identified.

摘要翻译： 虽然数据不能通过卡住的故障位置沿扫描链传输，但在卡住故障位置下游的正确操作的锁存器中的数据可以向下移动。 通过改变操作参数，例如电源和参考电压，时钟时序模式，温度和时序，可以触发从链路故障位置向下链接的一个或多个锁存器，以将状态从卡入故障值 。 然后运行SRL链将数据移出SRL链的输出。 输出被监视，并且从卡入状态的值的任何变化被注意为将所有良好的锁定位置识别到链的末端。 重复该过程：改变所选择的每个操作参数，直到识别出卡入故障锁存之后的锁存位置。

公开(公告)号：US07089474B2

公开(公告)日：2006-08-08

申请号：US10789710

申请日：2004-02-27

申请人： Todd M. Burdine ,  Franco Motika ,  Peilin Song

发明人： Todd M. Burdine ,  Franco Motika ,  Peilin Song

IPC分类号： G06F11/00 ,  G06F17/50

CPC分类号： G06F11/261 ,  G01R31/31703 ,  G01R31/318371 ,  G06F11/263

摘要： A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator. The method includes receiving a second failing region from the fault simulator, the second failing region created in response to the mismatches and the logic model, and the second failing region corresponding to a subset of the one or more circuits on the integrated circuit.

摘要翻译： 一种用于提供集成电路的交互式和迭代测试的方法，包括接收第一故障区域。 第一故障区域对应于集成电路上的一个或多个电路。 该方法响应于第一故障区域和集成电路的逻辑模型生成针对一个或多个电路的一组自适应算法测试模式。 确定测试模式的预期结果。 该方法包括将测试图案应用于集成电路上的第一故障区域，从而得到测试图案的实际结果。 对实际结果的预期结果进行比较。 该方法还将预期结果与实际结果之间的错配传输到故障模拟器。 该方法包括从故障模拟器接收第二故障区域，响应于不匹配和逻辑模型而创建的第二故障区域，以及对应于集成电路上的一个或多个电路的子集的第二故障区域。

公开(公告)号：US06662324B1

公开(公告)日：2003-12-09

申请号：US09642371

申请日：2000-08-21

申请人： Franco Motika ,  Richard F. Rizzolo ,  Peilin Song ,  William V. Huott ,  Ulrich Baur

发明人： Franco Motika ,  Richard F. Rizzolo ,  Peilin Song ,  William V. Huott ,  Ulrich Baur

IPC分类号： G01R3128

CPC分类号： G01R31/318525 ,  G01R31/31853 ,  G01R31/31858

摘要： The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function. In this design, the latch to be complemented does not require an additional input containing the complement value, but rather uses its current state as reference and switches to the opposite state. To accomplish this, a complement signal similar to a latch reset (i.e., reset-to-complement) can be used.

摘要翻译： 本发明能够在不改变另一个状态的情况下补充移位寄存器锁存器（SRL）中的主（L1）或从锁存器（L2）的状态。 当使用正常扫描链序列正确加载LSSD扫描链后，可以使用下一个系统时钟序列来启动扫描链中每个SRL所需的转换。 补充LSSD扫描链中锁存器状态的实际机制可以根据L1或L2锁存器中的哪一个进行补充而变化; 实际扫描链和Shift Register Latch（SRL）设计的细节; 和半导体芯片电路技术。 补充功能可以作为SRL设计的一个组成部分提供，对系统路径和性能影响最小。 一种替代的补充方法是使用自补充锁存功能。 在这种设计中，要补充的锁存器不需要包含补码值的附加输入，而是使用其当前状态作为参考，并切换到相反的状态。 为了实现这一点，可以使用类似于锁存器复位（即，复位到补码）的补码信号。

公开(公告)号：US20050188290A1

公开(公告)日：2005-08-25

申请号：US10780878

申请日：2004-02-19

申请人： Franco Motika ,  Peilin Song

发明人： Franco Motika ,  Peilin Song

IPC分类号： G01R31/28 ,  G01R31/311 ,  G01R31/3185

CPC分类号： G01R31/318547 ,  G01R31/311

摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.

摘要翻译： 测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环 通过电路的预定操作周期。

公开(公告)号：US06816990B2

公开(公告)日：2004-11-09

申请号：US10058485

申请日：2002-01-28

申请人： Peilin Song ,  Timothy J. Koprowski ,  Ulrich Baur ,  Franco Motika

发明人： Peilin Song ,  Timothy J. Koprowski ,  Ulrich Baur ,  Franco Motika

IPC分类号： G01R3128

CPC分类号： G01R31/31721 ,  G01R31/31707 ,  G01R31/318307 ,  G01R31/318502 ,  G01R31/318522 ,  G01R31/3187

摘要： LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.

摘要翻译： LBIST和加权LBIST测试在测试对象的不同部分上同时进行。 这种新的测试方法和设计变化与传统的测试策略相比，测试覆盖率和测试时间都大大降低。 它可以应用于晶圆，芯片，MCM和系统测试级别。 最重要的是，它不需要新的支持工具。 当前的测试软件将与传统的测试策略一样工作。 在相同测试会话中调度LBIST和加权LBIST测试降低了整体功耗，因为加权LBIST测试比平面LBIST测试消耗的功率少得多。 在相同的测试会话中，如果使用加权LBIST测试逻辑的某些部分，而使用LBIST测试其他部分，则电路元件在任何给定时间消耗的功率降低。

公开(公告)号：US07480882B1

公开(公告)日：2009-01-20

申请号：US12049344

申请日：2008-03-16

申请人： Peilin Song ,  David Heidel ,  Franco Motika ,  Franco Stellari

发明人： Peilin Song ,  David Heidel ,  Franco Motika ,  Franco Stellari

IPC分类号： G06F17/50 ,  G06F19/00 ,  G06F11/27 ,  G01R31/3187 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

摘要翻译： 该实施例取代了LBIST的使用以获得通过或不通过结果。 选择性签名功能用于通过在一个周期时间内抖动芯片来收集顶部故障路径。 这些路径可以片上或片外存储，供以后使用。 一旦芯片在现场运行一段时间，执行相同的过程来收集最上面的故障路径，并将其与存储的旧路径进行比较。 如果顶部路径的顺序发生变化，则表示（例如）有一个路径（不是最慢的路径）比其他路径慢，这可能是潜在的可靠性问题。 因此，在现场确定潜在的可靠性故障。

公开(公告)号：US07308626B2

公开(公告)日：2007-12-11

申请号：US10780878

申请日：2004-02-19

申请人： Franco Motika ,  Peilin Song

发明人： Franco Motika ,  Peilin Song

IPC分类号： G01R31/28

CPC分类号： G01R31/318547 ,  G01R31/311

摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.

摘要翻译： 测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环 通过电路的预定操作周期。

公开(公告)号：US20050204237A1

公开(公告)日：2005-09-15

申请号：US10789710

申请日：2004-02-27

申请人： Todd Burdine ,  Franco Motika ,  Peilin Song

发明人： Todd Burdine ,  Franco Motika ,  Peilin Song

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/261 ,  G01R31/31703 ,  G01R31/318371 ,  G06F11/263

摘要： A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator. The method includes receiving a second failing region from the fault simulator, the second failing region created in response to the mismatches and the logic model, and the second failing region corresponding to a subset of the one or more circuits on the integrated circuit.

摘要翻译： 一种用于提供集成电路的交互式和迭代测试的方法，包括接收第一故障区域。 第一故障区域对应于集成电路上的一个或多个电路。 该方法响应于第一故障区域和集成电路的逻辑模型生成针对一个或多个电路的一组自适应算法测试模式。 确定测试模式的预期结果。 该方法包括将测试图案应用于集成电路上的第一故障区域，从而得到测试图案的实际结果。 对实际结果的预期结果进行比较。 该方法还将预期结果与实际结果之间的错配传输到故障模拟器。 该方法包括从故障模拟器接收第二故障区域，响应于不匹配和逻辑模型而创建的第二故障区域，以及对应于集成电路上的一个或多个电路的子集的第二故障区域。

公开(公告)号：US06516432B1

公开(公告)日：2003-02-04

申请号：US09469699

申请日：1999-12-22

申请人： Franco Motika ,  Phillip J. Nigh ,  Peilin Song ,  Howard B. Druckerman

发明人： Franco Motika ,  Phillip J. Nigh ,  Peilin Song ,  Howard B. Druckerman

IPC分类号： G01R3128

CPC分类号： G01R31/318577

摘要： Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and comparing the output against an expected result. The system comprises identification phase, verifications and localization, and a characterization phases. The system is adaptable for use with on-board diagnostics and is adaptable for use with on-product clock generation systems.

摘要翻译： 公开了一种交流（AC）扫描诊断系统，其中一个或多个扫描链通过通过扫描链串行传播预定位图案并将输出与预期结果进行比较来测试。 该系统包括识别阶段，验证和定位以及特征化阶段。 该系统适用于车载诊断，适用于产品上的时钟发生系统。

公开(公告)号：US09069989B2

公开(公告)日：2015-06-30

申请号：US13360267

申请日：2012-01-27

申请人： Franco Motika ,  Dirk Pfeiffer ,  Peilin Song

发明人： Franco Motika ,  Dirk Pfeiffer ,  Peilin Song

IPC分类号： G06F21/73 ,  G01R31/3185 ,  G01R31/3183 ,  G06F7/58

CPC分类号： G01R31/3177 ,  G01R31/318328 ,  G01R31/318541 ,  G01R31/318547 ,  G06F7/588 ,  G06F21/73

摘要： Methods and systems for generating a circuit identification number include determining a propagation time delay across a scan chain of known length; comparing the propagation time delay to a threshold associated with the scan chain length; storing an identifier bit based on the result of the comparison; repeating the steps of determining, comparing, and storing until a number of stored identifier bits reaches a threshold number; and outputting the stored identifier bits.

摘要翻译： 用于产生电路识别号码的方法和系统包括确定跨越已知长度的扫描链的传播时间延迟; 将传播时间延迟与扫描链长度相关联的阈值进行比较; 基于比较结果存储标识符位; 重复确定，比较和存储的步骤，直到多个存储的标识符比特达到阈值数; 并输出所存储的标识符位。