公开(公告)号：US5781038A

公开(公告)日：1998-07-14

申请号：US597896

申请日：1996-02-05

Applicant: Krishnan Ramamurthy ,  Rong Pan ,  Ross MacTaggart ,  Francois Ducaroir

Inventor： Krishnan Ramamurthy ,  Rong Pan ,  Ross MacTaggart ,  Francois Ducaroir

IPC: G01R31/28 ,  H03K5/26 ,  H03L7/06 ,  H03K5/22

CPC classification number: G01R31/2882 ,  H03K5/26 ,  H03L7/06 ,  Y10S331/02

Abstract: A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).

Abstract translation: 一种用于在低于锁相环（13）的操作速度的测试频率下测试集成电路（12）中的高速锁相环（13）的装置和方法。 测试电路部分（10）重复测试来自锁相环（13）的恢复时钟信号（34）的零电平（42），并且锁存触发器（26）被设置为提供锁定指示输出（30 ），只要在测试时间（38）拍摄的重复采样继续指示恢复时钟信号（34）的零电平（42）。 测试时间（38）是从参考时钟输入（28）到集成电路（12）的外部源提供的参考时钟信号（36）的前沿（40）。

公开(公告)号：US5896426A

公开(公告)日：1999-04-20

申请号：US596978

申请日：1996-02-05

Applicant: Krishnan Ramamurthy ,  Marc Miller ,  Rong Pan ,  Francois Ducaroir

Inventor： Krishnan Ramamurthy ,  Marc Miller ,  Rong Pan ,  Francois Ducaroir

IPC: H04J3/06 ,  H04L7/00

CPC classification number: H04J3/0605 ,  H04L7/0004

Abstract: A character programming method (10) whereby a synchronization character (17) can be determined in a determine encoding scheme operation (12) and a determine synchronization character operation (14). The synchronization character (17) can then be programmed into a synch character logic (26) of an integrated circuit (20) or a core (20) thereof. The synch character logic (26) can be programmed through a plurality of program pins (30) on the periphery of the integrated circuit (20) or by more sophisticated means such as by sending the programming from a sending integrated circuit (40) to a receiving integrated circuit (42) through a communications line (44).

Abstract translation: 一种字符编程方法（10），由此可以在确定编码方案操作（12）和确定同步字符操作（14）中确定同步字符（17）。 然后，同步字符（17）可被编程到集成电路（20）或其核心（20）的同步字符逻辑（26）中。 同步字符逻辑（26）可以通过集成电路（20）的周边上的多个编程引脚（30）或更复杂的装置来编程，例如通过将编程从发送集成电路（40）发送到 通过通信线路（44）接收集成电路（42）。

公开(公告)号：US5956370A

公开(公告)日：1999-09-21

申请号：US586173

申请日：1996-01-17

Applicant: Francois Ducaroir ,  Rong Pan ,  Krishnan Ramamurthy

Inventor： Francois Ducaroir ,  Rong Pan ,  Krishnan Ramamurthy

IPC: H04L1/24 ,  H04B1/44

CPC classification number: H04L1/243 ,  H04Q2213/13036 ,  H04Q2213/1316 ,  H04Q2213/13162 ,  H04Q2213/13174 ,  H04Q2213/13213 ,  H04Q2213/1332 ,  H04Q2213/13322

Abstract: A wrap back test system and method for providing local fault detection within a section of an integrated I/O interface core device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The wrap back of input test data, prior to reformatting for transmission, to the receiver's data alignment stage permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the wrap back of alignment pattern encoded parallel data, prior to serialization, to the receiver's data alignment stage permits identifying faults in just this portion of the I/O transceiver. The wrap back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Abstract translation: 公开了一种用于在集成电路上的集成I / O接口核心器件的部分内提供本地故障检测的回绕测试系统和方法。 本发明的系统和方法适用于具有发射机和接收机部分的任何I / O接口。 在将重新格式化传输之前，输入测试数据的回绕到接收机的数据对准阶段允许在集成I / O接口的核心内进行故障检测。 通过图示，在串行器/解串器I / O中，在序列化之前将对准模式编码并行数据的回绕到接收机的数据对准阶段允许在I / O收发器的这一部分中识别故障。 本发明的回绕测试系统和方法允许在I / O核心的边界内的故障隔离，而与外部逻辑或测试器无关。

公开(公告)号：US5790563A

公开(公告)日：1998-08-04

申请号：US879673

申请日：1997-06-23

Applicant: Krishnan Ramamurthy ,  Rong Pan ,  Francois Ducaroir

Inventor： Krishnan Ramamurthy ,  Rong Pan ,  Francois Ducaroir

IPC: G01R31/317 ,  G01R31/3181 ,  G01R31/3185 ,  G06F11/00

CPC classification number: G01R31/31716 ,  G01R31/31715 ,  G01R31/3185 ,  G01R31/31813

Abstract: A test method and means for in integrated circuit (10) having asynchronous communication capabilities including a transmitter (12) and a receiver (14). A pattern generator (24) is provided for generating patterns directly from within the integrated circuit (10). In the best presently known embodiment, a serializer (16) provides a serial output (20) and a deserializer (18) processes a serial input (22) into a parallel signal and provides the parallel signal to a receiver (14). The pattern generator (24) is preprogrammed to provide a parallel data pattern which can optionally and intermittently be provided to the transmitter (12) in a test mode (44). In the test mode (44), signal is routed from the serializer (16) directly to the deserializer (18) via an external loop back path (34) or an internal alternative loop back path (34a). When in the test mode, comparison unit (38) internally generates a pattern identical to that produced by the pattern generator (24) and locks onto signal received from the receiver (14) to perform a functional test (54) and an optional parametric test (58).

Abstract translation: 一种具有包括发射器（12）和接收器（14）的异步通信能力的集成电路（10）的测试方法和装置。 提供了一种图形生成器（24），用于直接从集成电路（10）内产生图案。 在最好的已知实施例中，串行器（16）提供串行输出（20）和解串行器（18）将串行输入（22）处理成并行信号并将并行信号提供给接收器（14）。 图案生成器（24）被预编程以提供在测试模式（44）中可选地和间歇地提供给发射器（12）的并行数据模式。 在测试模式（44）中，信号通过外部回路路径（34）或内部替代回路（34a）从串行器（16）直接传送到解串器（18）。 当在测试模式中，比较单元（38）在内部生成与由模式发生器（24）生成的模式相同的模式，并锁定从接收器（14）接收到的信号，以进行功能测试（54）和可选的参数测试 （58）。

公开(公告)号：US5787114A

公开(公告)日：1998-07-28

申请号：US586174

申请日：1996-01-17

Applicant: Krishnan Ramamurthy ,  Rong Pan ,  Francois Ducaroir

Inventor： Krishnan Ramamurthy ,  Rong Pan ,  Francois Ducaroir

IPC: G06F11/267 ,  H04L1/24 ,  H04B1/44

CPC classification number: G06F11/2221 ,  H04L1/241 ,  H04L1/243

Abstract: A loop back test system and method for providing local fault detection within the core or macrocell of an integrated I/O interface device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The loop back of input test data from the transmitters output directly to the receiver's input permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the loop back of serialized, alignment pattern encoded parallel data from the output stage of the I/O transmitter to the receiver's input stage permits identifying faults occurring within the integrated I/O transceiver macrocell. The loop back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Abstract translation: 公开了一种用于在集成电路上的集成I / O接口设备的核心或宏小区内提供本地故障检测的环回测试系统和方法。 本发明的系统和方法适用于具有发射机和接收机部分的任何I / O接口。 输出测试数据从发射机直接输出到接收机输入的回路允许在集成I / O接口的核心内进行故障检测。 通过图示，在串行器/解串器I / O中，从I / O发射器的输出级到接收器的输入级的串行化对准模式编码并行数据的回送允许识别在集成I / O收发器宏单元内发生的故障 。 本发明的环回测试系统和方法允许在I / O核心的边界内进行故障隔离，而与外部逻辑或测试器无关。