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1.发明授权Apparatus and method for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency 失效用于测试一对串行数据收发器以一个频率传输串行数据并以另一频率接收串行数据的能力的装置和方法公开(公告)号：US06208621B1
公开(公告)日：2001-03-27
申请号：US08991906
申请日：1997-12-16
IPC分类号： H04L1226
摘要： An apparatus and method are presented for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency. A serial communication device of the present invention includes a first and second serial data transceivers and a multiplexer formed upon a monolithic semiconductor substrate. Each serial data transceiver includes a receiver and a transmitter which transmits serial data in response to a clock signal. The second serial data transceiver is coupled to receive a reference clock signal. The multiplexer facilitates testing, and is coupled to the first serial data transceiver. The multiplexer receives the reference clock signal, a test clock signal, and a test signal, and provides either the reference clock signal or the test clock signal to the first transceiver dependent upon the test signal. The reference and test clock signals have different frequencies. The multiplexer provides the reference clock signal to the first transceiver when the test signal is deasserted, and provides the test clock signal to the first transceiver when the test signal is asserted. During testing, the output of the transmitter of one transceiver is coupled to the input of the receiver of the other transceiver, and the test signal is asserted. Each receiver produces parallel output test data. A match between the two sets of parallel output test data and the parallel input test data demonstrates the abilities of both transceivers to transmit and receive serial data at different frequencies.
摘要翻译： 提出了一种用于测试一对串行数据收发器以一个频率传输串行数据并以另一频率接收串行数据的能力的装置和方法。 本发明的串行通信设备包括第一和第二串行数据收发器以及形成在单片半导体衬底上的多路复用器。 每个串行数据收发器包括一个接收器和一个响应时钟信号发送串行数据的发送器。 第二串行数据收发器被耦合以接收参考时钟信号。 多路复用器便于测试，并且耦合到第一串行数据收发器。 多路复用器接收参考时钟信号，测试时钟信号和测试信号，并根据测试信号将参考时钟信号或测试时钟信号提供给第一收发器。 参考和测试时钟信号具有不同的频率。 当测试信号被断言时，多路复用器将参考时钟信号提供给第一收发器，并且当测试信号被断言时，将测试时钟信号提供给第一收发器。 在测试期间，一个收发器的发射机的输出耦合到另一个收发器的接收机的输入，并且测试信号被断言。 每个接收机产生并行输出测试数据。 两组并行输出测试数据和并行输入测试数据之间的匹配表明两个收发器在不同频率下发送和接收串行数据的能力。
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2.发明授权Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream 失效用于测量串行数据流中抖动量的串行数据收发器架构和测试方法公开(公告)号：US06331999B1
公开(公告)日：2001-12-18
申请号：US09007490
申请日：1998-01-15
IPC分类号： H04B346
CPC分类号： H04J3/047 , H03L7/099 , H03L7/0995 , H04L1/205 , H04L7/033
摘要： A serial data transceiver architecture and test method are presented for measuring the amount of jitter within a serial data stream. A transmitter of the transceiver receives parallel input data at a transmit data input port, converts the parallel input data to a serial data stream having data windows separated by data transition periods, and produces the serial data stream at a transmitter output port. A receiver of the transceiver receives a serial data stream at a receiver input port, converts the serial data stream to parallel output data, and provides the parallel output data at a receive data output port. The receiver includes a deserializer which receives the serial data stream, recovers the transmit clock signal used to transmit the serial data from the serial data stream, generates a timing signal based upon the recovered transmit clock signal, samples the serial data stream using the timing signal in order to recover the data from the serial data stream, aligns the deserialized data into parallel units, and provides the resulting parallel data at the receive data output port. The deserializer samples the serial data stream within each data window dependent upon the duty cycle of the timing signal. The deserializer varies the duty cycle of the timing signal according to a received control signal in order to facilitate measurement of the amount of jitter within the serial data stream.
摘要翻译： 提出了串行数据收发器架构和测试方法，用于测量串行数据流中的抖动量。 收发器的发射机在发射数据输入端口处接收并行输入数据，将并行输入数据转换为具有由数据转换周期分隔的数据窗口的串行数据流，并在发射机输出端口产生串行数据流。 收发器的接收器在接收器输入端口接收串行数据流，将串行数据流转换为并行输出数据，并在接收数据输出端口提供并行输出数据。 接收机包括接收串行数据流的解串器，恢复用于从串行数据流发送串行数据的发送时钟信号，基于恢复的发送时钟信号产生定时信号，使用定时信号对串行数据流进行采样 为了从串行数据流中恢复数据，将反序列化数据对齐为并行单元，并在接收数据输出端口提供所得到的并行数据。 解串器根据定时信号的占空比对每个数据窗口内的串行数据流进行采样。 解串器根据接收到的控制信号改变定时信号的占空比，以便于测量串行数据流内的抖动量。
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公开(公告)号：US6085257A
公开(公告)日：2000-07-04
申请号：US951896
申请日：1997-10-16
CPC分类号： G09G5/006 , G09G2370/04
摘要： An improved transceiver that is tightly integrated into an enhanced receiving chip for a computer monitor. The transceiver includes a receiver having a first input port for receiving serialized data, a first output port for transmitting deserialized data to the transceiver, and a second input port adapted for receiving feedback data forwarded from a sensor to an audio and video control unit. The serialized data comprises video, audio and control data. The transceiver further comprises a receiver operably coupled between the first input port and the first output port, as well as a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. The transceiver also includes a transmitter with a third input port for receiving parallel data and a second output port for transmitting a serial data stream. The parallel data are received by the third input port concurrently with the serialized data being received by the first input port. A deserializer is coupled to convert the serialized data into the deserialized data. A serializer is coupled to convert the parallel data into the serial data stream. The transceiver is also part of a communications module, adapted for use in a monitor, also including a timing generator for generating a clock for synchronized timing, control registers for storing native format control data, and a sound generator for producing audio signals which correspond to native format audio data sent to the communications module from a base computer.
摘要翻译： 一种改进的收发器，紧密集成到用于计算机监视器的增强型接收芯片中。 收发器包括具有用于接收串行数据的第一输入端口的接收器，用于将反序列化数据发送到收发器的第一输出端口以及适于接收从传感器转发到音频和视频控制单元的反馈数据的第二输入端口。 串行数据包括视频，音频和控制数据。 所述收发器还包括可操作地耦合在所述第一输入端口和所述第一输出端口之间的接收器以及被连接以从所述串行化数据恢复时钟信号并使来自恢复时钟的反序列化数据同步的定时发生器。 收发器还包括具有用于接收并行数据的第三输入端口的发射器和用于发送串行数据流的第二输出端口。 并行数据由第三输入端口与由第一输入端口接收的串行化数据同时接收。 解串器耦合以将序列化数据转换为反序列化数据。 串行器被耦合以将并行数据转换成串行数据流。 收发器也是适用于监视器的通信模块的一部分，还包括用于产生用于同步定时的时钟的定时发生器，用于存储本地格式控制数据的控制寄存器，以及用于产生对应于 从基本计算机发送到通信模块的原始格式音频数据。
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4.发明授权Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method 失效串行数据收发器包括便于仅访问串行数据端口的功能测试的元件，以及相关的测试方法公开(公告)号：US06341142B2
公开(公告)日：2002-01-22
申请号：US08991715
申请日：1997-12-16
IPC分类号： H04L516
CPC分类号： H04B3/46
摘要： A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter. As a result, the received serial data is retransmitted by the transceiver. A test method involves asserting the test signal, providing serial input test data to a serial data input port, receiving serial output test data from a serial data output port, and comparing the serial output test data to the serial input test data. A match between the serial output test data and the serial input test data verifies proper operation of the serial data transceiver.
摘要翻译： 提出了一种串行数据收发器，其包括仅使用收发器的串行数据传输终端进行测试的元件。 串行数据收发器包括发射机和接收机。 发送器接收并行数据，将并行数据转换为串行数据流，并发送串行数据流。 接收器接收串行数据流，将串行数据流转换为并行数据，并提供并行数据。 在测试期间，由接收机产生的并行数据被路由到发射机输入。 在一个实施例中，发射机包括用于将并行输入数据路由到发射机的第一路由器，并且接收机包括用于路由由接收机产生的并行输出数据的第二路由器。 第一路由器耦合到第二路由器，两个路由器都接收测试信号。 当测试信号被断言时，第二路由器将由接收机产生的并行输出数据路由到第一路由器，并且第一路由器将由接收机产生的并行输出数据路由到发射机。 结果，接收到的串行数据由收发器重传。 测试方法包括断言测试信号，向串行数据输入端口提供串行输入测试数据，从串行数据输出端口接收串行输出测试数据，以及将串行输出测试数据与串行输入测试数据进行比较。 串行输出测试数据和串行输入测试数据之间的匹配验证串行数据收发器的正确操作。
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5.发明授权High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network 失效高速串行线收发器集成到高速缓存控制器中，以支持松散耦合网络中的一致存储器事务公开(公告)号：US06330591B1
公开(公告)日：2001-12-11
申请号：US09036897
申请日：1998-03-09
IPC分类号： G06F1338
CPC分类号： G06F12/0815 , G06F12/0813 , G06F12/0817
摘要： One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent. Each transmit unit comprises a receiver operably coupled between an input port and an output port, and a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. Also included are a transmitter which receives parallel data and transmits a serial data stream. The parallel data are received concurrently with the serialized data being received. A deserializer is coupled to convert the serialized data into the deserialized data. A serializer is coupled to convert the parallel data into the serial data stream.
摘要翻译： 一个或多个改进的发射单元与控制器紧密集成到增强型集群高速缓存中。 通过将所有计算机连接到所有其他计算机的高速，低延迟和高带宽串行线路将松散耦合的计算机网络中的所有计算机发送所有缓存更新，从而支持松散耦合的计算机网络中的相干内存事务。 集群高速缓存控制器可以包括本地高速缓存控制器和/或作为本地总线控制器。 本地总线控制器可操作以将集群高速缓存耦合到I / O子系统。 本地高速缓冲存储器优选地为整个计算机高速缓存数据和/或指令或其位置，使得本地计算机缓存可通过发送单元对整个计算机集群可用。 每个传输单元是一个全双工收发器，包括发射机和接收机功能。 每个传送单元可以同时发送和接收数据，因为其发射机和接收机功能的操作是独立的。 每个发射单元包括可操作地耦合在输入端口和输出端口之间的接收器，以及连接到从串行化数据恢复时钟信号并使来自恢复时钟的反序列化数据同步的定时发生器。 还包括接收并行数据并发送串行数据流的发送器。 与正在接收的序列化数据同时接收并行数据。 解串器耦合以将序列化数据转换为反序列化数据。 串行器被耦合以将并行数据转换成串行数据流。
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公开(公告)号：US5781038A
公开(公告)日：1998-07-14
申请号：US597896
申请日：1996-02-05
CPC分类号： G01R31/2882 , H03K5/26 , H03L7/06 , Y10S331/02
摘要： A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).
摘要翻译： 一种用于在低于锁相环（13）的操作速度的测试频率下测试集成电路（12）中的高速锁相环（13）的装置和方法。 测试电路部分（10）重复测试来自锁相环（13）的恢复时钟信号（34）的零电平（42），并且锁存触发器（26）被设置为提供锁定指示输出（30 ），只要在测试时间（38）拍摄的重复采样继续指示恢复时钟信号（34）的零电平（42）。 测试时间（38）是从参考时钟输入（28）到集成电路（12）的外部源提供的参考时钟信号（36）的前沿（40）。
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7.发明授权System for sending data from-and-to a computer monitor using a high speed serial line 失效使用高速串行线路将数据发送到计算机显示器的系统
公开(公告)号：US6061747A
公开(公告)日：2000-05-09
申请号：US951530
申请日：1997-10-16
CPC分类号： G09G5/006 , G09G2370/04 , G09G5/008
摘要： An improved transceiver pair that are tightly integrated into a computer system. The transceiver pair include a base transceiver and a remote transceiver, with a high speed serial connection between them. The base transceiver has a base transmitter with a parallel input port for accepting parallel, encoded data and a serial output port for transmitting a serial, encoded data stream. The remote transceiver has a receiver with a serial input port for receiving the serial, encoded data stream and an audio/video output port for passing deserialized data to an audio and video control unit after decoding. The high speed serial connection links the base serial output port to the remote serial input port. The remote receiver further includes a feedback input port adapted for receiving feedback data forwarded from a sensor. The sensor may respond to palpable, optical or sonic input or to physical contact. The computer system may include the remote transceiver for transmitting a return serial data stream, a transmitter operably coupled between the feedback input port and the remote serial output port, and a timing generator coupled to recover a clock signal from the serial data stream and to synchronize the deserialized data. The base transceiver may also include a serial input port for receiving the return serial data stream, a receiver operably coupled to the serial input port, and a return high speed serial connection between the remote serial output port and the base serial input port. The return serial data stream is received concurrent with the serial data stream being received.
摘要翻译： 改进的收发器对，紧密集成到计算机系统中。 收发器对包括基地收发器和远程收发器，它们之间具有高速串行连接。 基地收发器具有基本发射机，具有用于接受并行编码数据的并行输入端口和用于发送串行编码数据流的串行输出端口。 远程收发器具有接收器，其具有用于接收串行编码数据流的串行输入端口和用于在解码之后将反序列化数据传送到音频和视频控制单元的音频/视频输出端口。 高速串行连接将基本串行输出端口连接到远程串行输入端口。 远程接收器还包括适于接收从传感器转发的反馈数据的反馈输入端口。 传感器可能响应可触及，光学或声音输入或物理接触。 计算机系统可以包括用于发送返回串行数据流的远程收发器，可操作地耦合在反馈输入端口和远程串行输出端口之间的发送器以及耦合以从串行数据流恢复时钟信号并同步的定时发生器 反序列化数据。 基本收发器还可以包括用于接收返回串行数据流的串行输入端口，可操作地耦合到串行输入端口的接收器以及远程串行输出端口和基本串行输入端口之间的返回高速串行连接。 与正在接收的串行数据流同时接收返回串行数据流。
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公开(公告)号：US5956370A
公开(公告)日：1999-09-21
申请号：US586173
申请日：1996-01-17
申请人： Francois Ducaroir , Rong Pan , Krishnan Ramamurthy
发明人： Francois Ducaroir , Rong Pan , Krishnan Ramamurthy
CPC分类号： H04L1/243 , H04Q2213/13036 , H04Q2213/1316 , H04Q2213/13162 , H04Q2213/13174 , H04Q2213/13213 , H04Q2213/1332 , H04Q2213/13322
摘要： A wrap back test system and method for providing local fault detection within a section of an integrated I/O interface core device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The wrap back of input test data, prior to reformatting for transmission, to the receiver's data alignment stage permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the wrap back of alignment pattern encoded parallel data, prior to serialization, to the receiver's data alignment stage permits identifying faults in just this portion of the I/O transceiver. The wrap back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.
摘要翻译： 公开了一种用于在集成电路上的集成I / O接口核心器件的部分内提供本地故障检测的回绕测试系统和方法。 本发明的系统和方法适用于具有发射机和接收机部分的任何I / O接口。 在将重新格式化传输之前，输入测试数据的回绕到接收机的数据对准阶段允许在集成I / O接口的核心内进行故障检测。 通过图示，在串行器/解串器I / O中，在序列化之前将对准模式编码并行数据的回绕到接收机的数据对准阶段允许在I / O收发器的这一部分中识别故障。 本发明的回绕测试系统和方法允许在I / O核心的边界内的故障隔离，而与外部逻辑或测试器无关。
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公开(公告)号：US5790563A
公开(公告)日：1998-08-04
申请号：US879673
申请日：1997-06-23
申请人： Krishnan Ramamurthy , Rong Pan , Francois Ducaroir
发明人： Krishnan Ramamurthy , Rong Pan , Francois Ducaroir
IPC分类号： G01R31/317 , G01R31/3181 , G01R31/3185 , G06F11/00
CPC分类号： G01R31/31716 , G01R31/31715 , G01R31/3185 , G01R31/31813
摘要： A test method and means for in integrated circuit (10) having asynchronous communication capabilities including a transmitter (12) and a receiver (14). A pattern generator (24) is provided for generating patterns directly from within the integrated circuit (10). In the best presently known embodiment, a serializer (16) provides a serial output (20) and a deserializer (18) processes a serial input (22) into a parallel signal and provides the parallel signal to a receiver (14). The pattern generator (24) is preprogrammed to provide a parallel data pattern which can optionally and intermittently be provided to the transmitter (12) in a test mode (44). In the test mode (44), signal is routed from the serializer (16) directly to the deserializer (18) via an external loop back path (34) or an internal alternative loop back path (34a). When in the test mode, comparison unit (38) internally generates a pattern identical to that produced by the pattern generator (24) and locks onto signal received from the receiver (14) to perform a functional test (54) and an optional parametric test (58).
摘要翻译： 一种具有包括发射器（12）和接收器（14）的异步通信能力的集成电路（10）的测试方法和装置。 提供了一种图形生成器（24），用于直接从集成电路（10）内产生图案。 在最好的已知实施例中，串行器（16）提供串行输出（20）和解串行器（18）将串行输入（22）处理成并行信号并将并行信号提供给接收器（14）。 图案生成器（24）被预编程以提供在测试模式（44）中可选地和间歇地提供给发射器（12）的并行数据模式。 在测试模式（44）中，信号通过外部回路路径（34）或内部替代回路（34a）从串行器（16）直接传送到解串器（18）。 当在测试模式中，比较单元（38）在内部生成与由模式发生器（24）生成的模式相同的模式，并锁定从接收器（14）接收到的信号，以进行功能测试（54）和可选的参数测试 （58）。
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公开(公告)号：US5787114A
公开(公告)日：1998-07-28
申请号：US586174
申请日：1996-01-17
申请人： Krishnan Ramamurthy , Rong Pan , Francois Ducaroir
发明人： Krishnan Ramamurthy , Rong Pan , Francois Ducaroir
IPC分类号： G06F11/267 , H04L1/24 , H04B1/44
CPC分类号： G06F11/2221 , H04L1/241 , H04L1/243
摘要： A loop back test system and method for providing local fault detection within the core or macrocell of an integrated I/O interface device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The loop back of input test data from the transmitters output directly to the receiver's input permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the loop back of serialized, alignment pattern encoded parallel data from the output stage of the I/O transmitter to the receiver's input stage permits identifying faults occurring within the integrated I/O transceiver macrocell. The loop back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.
摘要翻译： 公开了一种用于在集成电路上的集成I / O接口设备的核心或宏小区内提供本地故障检测的环回测试系统和方法。 本发明的系统和方法适用于具有发射机和接收机部分的任何I / O接口。 输出测试数据从发射机直接输出到接收机输入的回路允许在集成I / O接口的核心内进行故障检测。 通过图示，在串行器/解串器I / O中，从I / O发射器的输出级到接收器的输入级的串行化对准模式编码并行数据的回送允许识别在集成I / O收发器宏单元内发生的故障 。 本发明的环回测试系统和方法允许在I / O核心的边界内进行故障隔离，而与外部逻辑或测试器无关。
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