公开(公告)号：US20080206973A1

公开(公告)日：2008-08-28

申请号：US11710769

申请日：2007-02-26

申请人： Frank Scott Johnson ,  Freidoon Mehrad ,  Jiong-Ping Lu

发明人： Frank Scott Johnson ,  Freidoon Mehrad ,  Jiong-Ping Lu

IPC分类号： H01L21/3205

CPC分类号： H01L21/26506 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

摘要： An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming oxide and nitride etch-stop layers over a top portion of the gates of the NMOS and PMOS transistors, forming a blocking layer over the etch-stop layer, planarizing the blocking layer down to the etch-stop layer over the gates, and removing a portion of the etch-stop layer overlying the gates. The method further includes implanting a preamorphizing species into the exposed gates to amorphize the gates, thereby permitting uniform silicide formation thereafter at substantially the same rates in the NMOS and PMOS transistors. The method may further comprise removing any remaining oxide or blocking layers, forming the gate silicide over the gates to form the FUSI gates, and forming source/drain silicide in moat areas of the NMOS and PMOS transistors.

摘要翻译： 公开了在相同MOS器件的NMOS和PMOS晶体管中形成完全硅化（FUSI）栅极的改进方法。 在一个示例中，该方法包括在NMOS和PMOS晶体管的栅极的顶部部分上形成氧化物和氮化物蚀刻停止层，在蚀刻停止层上形成阻挡层，将阻挡层平坦化到蚀刻停止 并且去除覆盖在栅极上的蚀刻停止层的一部分。 该方法还包括将预变质物质注入到暴露的栅极中以使栅极非晶化，从而在NMOS和PMOS晶体管中以基本上相同的速率允许均匀的硅化物形成。 该方法还可以包括去除任何剩余的氧化物或阻挡层，在栅极上形成栅极硅化物以形成FUSI栅极，以及在NMOS和PMOS晶体管的护环区域中形成源极/漏极硅化物。

公开(公告)号：US07448395B2

公开(公告)日：2008-11-11

申请号：US10894374

申请日：2004-07-19

申请人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

发明人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

IPC分类号： B08B6/00 ,  C25F1/00 ,  C25F3/30 ,  C25F5/00

CPC分类号： H01L21/28518 ,  H01L21/02046 ,  H01L21/0206 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.

摘要翻译： 本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。 随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。 残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。 通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。 第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。 延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

公开(公告)号：US20080265345A1

公开(公告)日：2008-10-30

申请号：US12135910

申请日：2008-06-09

申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

IPC分类号： H01L49/00

CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

公开(公告)号：US20080265420A1

公开(公告)日：2008-10-30

申请号：US11741540

申请日：2007-04-27

申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

IPC分类号： H01L21/3205 ,  H01L23/48

CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

公开(公告)号：US07585738B2

公开(公告)日：2009-09-08

申请号：US11741540

申请日：2007-04-27

申请人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

发明人： Shaofeng Yu ,  Freidoon Mehrad ,  Jiong-Ping Lu

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28097 ,  H01L29/66507 ,  H01L29/66545

摘要： A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

摘要翻译： 一种形成具有独立栅极和源极/漏极掺杂及相关器件的完全硅化半导体器件的方法。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法（包括多晶硅层和阻挡层的栅极堆叠），以及执行离子注入到与栅极堆叠相邻的衬底的有源区域中 阻挡层基本上阻挡从多晶硅层的离子注入）。

公开(公告)号：US20080176345A1

公开(公告)日：2008-07-24

申请号：US11655483

申请日：2007-01-19

申请人： Shaofeng Yu ,  Richard L. Guldi ,  Jiong-Ping Lu ,  Freidoon Mehrad ,  Jae Hyun Park

发明人： Shaofeng Yu ,  Richard L. Guldi ,  Jiong-Ping Lu ,  Freidoon Mehrad ,  Jae Hyun Park

IPC分类号： H01L21/66

CPC分类号： H01L22/14

摘要： Gate dielectric punch through and/or incomplete silicidation or metallization events that may occur during transistor formation are identified. The events are identified just after gate electrodes are formed in order to characterize the degree of faulty transistors for process control purposes and to scrap product if sufficiently defective so that subsequent resources are not unnecessarily expended. An electron beam or ebeam is directed at locations of a workpiece whereon on or more transistors are formed. Electrons that are resultantly emitted from these locations are detected and used to develop respective gray level values (GLV's). Gate dielectric punch through and/or incomplete silicidation or metallization events are identified by finding high or low GLV's relative to neighboring areas.

摘要翻译： 识别在晶体管形成期间可能发生的栅极电介质穿透和/或不完全的硅化或金属化事件。 在形成栅极电极之后才识别事件，以便表征用于过程控制目的的故障晶体管的程度，并且如果充分有缺陷，则废弃产品，使得后续资源不会被不必要地消耗。 电子束或ebeam被引导到其上形成有多个晶体管的工件的位置。 从这些位置发射的电子被检测并用于开发各自的灰度值（GLV's）。 通过相对于相邻区域发现高或低GLV来鉴定栅极电介质穿透和/或不完全硅化或金属化事件。

公开(公告)号：US20060014393A1

公开(公告)日：2006-01-19

申请号：US10894374

申请日：2004-07-19

申请人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

发明人： Jiong-Ping Lu ,  Freidoon Mehrad ,  Lindsey Hall ,  Vivian Liu ,  Clint Montgomery ,  Scott Johnson

IPC分类号： H01L21/302

CPC分类号： H01L21/28518 ,  H01L21/02046 ,  H01L21/0206 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.

摘要翻译： 本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。 随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。 残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。 通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。 第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。 延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

公开(公告)号：US07994073B2

公开(公告)日：2011-08-09

申请号：US11940433

申请日：2007-11-15

申请人： Jiong-Ping Lu ,  Periannan Chidambaram ,  Srinivasan Chakravarthi

发明人： Jiong-Ping Lu ,  Periannan Chidambaram ,  Srinivasan Chakravarthi

IPC分类号： H01L21/31

CPC分类号： H01L21/26513 ,  H01L21/3185 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/6659

摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.

摘要翻译： 具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120。 或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410.而且，用于制造具有低应力牺牲帽层120,410的晶体管40,400的方法300,500。

公开(公告)号：US07732852B2

公开(公告)日：2010-06-08

申请号：US11499308

申请日：2006-08-03

申请人： Jiong-Ping Lu ,  Ming-Jang Hwang

发明人： Jiong-Ping Lu ,  Ming-Jang Hwang

IPC分类号： H01L27/108

CPC分类号： C23C16/34 ,  C23C16/56 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31683 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/57

摘要： High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.

摘要翻译： 通过相应氮化物的顺序化学气相沉积（CVD）形成钛和钨或钛和钽的混合过渡金属氧化物的高介电膜，并在氧的存在下退火以致密化和氧化氮化物。 所得到的膜可用作电容性电池并且抵抗向下层材料的氧扩散，具有高电容和低电流泄漏。

公开(公告)号：US07666729B2

公开(公告)日：2010-02-23

申请号：US11456595

申请日：2006-07-11

申请人： Jiong-Ping Lu ,  Jiejie Xu

发明人： Jiong-Ping Lu ,  Jiejie Xu

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/28052 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an interface layer 200 over the semiconductor substrate 20 and performing an anneal to create a silicide 190 on the top surface of the gate electrode 110.

摘要翻译： 本发明的一个实施例是通过在栅电极层110上执行离子注入来制造晶体管的方法。该方法可以包括在半导体衬底20上形成界面层200并执行退火以在顶部形成硅化物190 栅电极110的表面。