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    Lateral DMOS transistor and method for the production thereof
    5.
    发明申请
    Lateral DMOS transistor and method for the production thereof 失效
    侧面DMOS晶体管及其制造方法

    公开(公告)号：US20070235779A1

    公开(公告)日：2007-10-11

    申请号：US11730514

    申请日：2007-04-02

    申请人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

    发明人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

    IPC分类号： H01L29/76 ,  H01L21/8234

    CPC分类号： H01L29/66659 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

    摘要翻译： 提供了一种横向DMOS晶体管，其包括由第一导电类型的半导体材料制成的MOS二极管，第二导电类型的源极区域和第二导电类型的漏极区域，其为 通过由第二导电类型的半导体材料制成的漂移区域与MOS二极管分开，所述漂移区域至少部分被还覆盖MOS二极管的半导体材料的介电栅极层覆盖。 介电栅极层包括第一厚度的第一区域和第二厚度的第二区域。 第一区域覆盖MOS二极管的半导体材料，第二区域布置在漂移区域上。 从第一厚度到第二厚度发生转变，使得朝向MOS二极管定向的漂移区的边缘区域布置在栅极层的第二区域的下方。 本发明还涉及一种用于生产这些类型的DMOS晶体管的方法。

    REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS
    6.
    发明申请
    REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS 审中-公开
    注册区域内的注册标志

    公开(公告)号：US20070207589A1

    公开(公告)日：2007-09-06

    申请号：US11744992

    申请日：2007-05-07

    申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Stefan Schwantes ,  Gayle Miller

    发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Stefan Schwantes ,  Gayle Miller

    IPC分类号： H01L21/76

    CPC分类号： G03F7/70425 ,  G03F7/70633 ,  G03F9/7076

    摘要： A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

    摘要翻译： 在双井集成电路技术中的第一标记是通过在ONO堆叠的顶部上的第一掩模层的第一蚀刻形成的。 在第一阱被掺杂之后，在ONO堆叠的最上层的氧化物的第一蚀刻位置处发生第二蚀刻，形成第一对准伪影。 在去除第一掩模层之后施加第二掩模层。 第二阱掺杂发生在第二掩模层蚀刻位置处，以保持有效区域内的两个阱之间的间隙，并且在框架区域中提供两个阱的重叠。 在两个阱的重叠处的第一对准伪影处，进一步蚀刻去除ONO堆叠的剩余层，并从半导体层的最上层去除硅，形成可被保护层覆盖的第二对准标记。

    Lateral DMOS transistor and method for the production thereof
    7.
    发明授权
    Lateral DMOS transistor and method for the production thereof 失效
    侧面DMOS晶体管及其制造方法

    公开(公告)号：US07973333B2

    公开(公告)日：2011-07-05

    申请号：US11730514

    申请日：2007-04-02

    申请人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

    发明人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66659 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

    摘要翻译： 提供了一种横向DMOS晶体管，其包括由第一导电类型的半导体材料制成的MOS二极管，第二导电类型的源极区域和第二导电类型的漏极区域，其为 通过由第二导电类型的半导体材料制成的漂移区域与MOS二极管分开，所述漂移区域至少部分被还覆盖MOS二极管的半导体材料的介电栅极层覆盖。 介电栅极层包括第一厚度的第一区域和第二厚度的第二区域。 第一区域覆盖MOS二极管的半导体材料，第二区域布置在漂移区域上。 从第一厚度到第二厚度发生转变，使得朝向MOS二极管定向的漂移区的边缘区域布置在栅极层的第二区域的下方。 本发明还涉及一种用于生产这些类型的DMOS晶体管的方法。

    Registration mark within an overlap of dopant regions
    8.
    发明申请
    Registration mark within an overlap of dopant regions 有权
    掺杂区域重叠内的对准标记

    公开(公告)号：US20070048959A1

    公开(公告)日：2007-03-01

    申请号：US11217250

    申请日：2005-08-31

    申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Stefan Schwantes ,  Gayle Miller

    发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Stefan Schwantes ,  Gayle Miller

    IPC分类号： H01L21/331

    CPC分类号： G03F7/70425 ,  G03F7/70633 ,  G03F9/7076

    摘要： A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

    摘要翻译： 在双井集成电路技术中的第一标记是通过在ONO堆叠的顶部上的第一掩模层的第一蚀刻形成的。 在第一阱被掺杂之后，在ONO堆叠的最上层的氧化物的第一蚀刻位置处发生第二蚀刻，形成第一对准伪影。 在去除第一掩模层之后施加第二掩模层。 第二阱掺杂发生在第二掩模层蚀刻位置处，以保持有效区域内的两个阱之间的间隙，并且在框架区域中提供两个阱的重叠。 在两个阱的重叠处的第一对准伪影处，进一步蚀刻去除ONO堆叠的剩余层，并从半导体层的最上层去除硅，形成可被保护层覆盖的第二对准标记。

    Methods of forming reduced electric field DMOS using self-aligned trench isolation
    9.
    发明授权
    Methods of forming reduced electric field DMOS using self-aligned trench isolation 有权
    使用自对准沟槽隔离形成还原电场DMOS的方法

    公开(公告)号：US07348256B2

    公开(公告)日：2008-03-25

    申请号：US11188921

    申请日：2005-07-25

    申请人： Gayle W. Miller, Jr. ,  Volker Dudek ,  Michael Graf

    发明人： Gayle W. Miller, Jr. ,  Volker Dudek ,  Michael Graf

    IPC分类号： H01L21/76

    CPC分类号： H01L29/7824 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

    摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

    摘要翻译： 一种制造电子装置的方法和所得到的电子装置。 该方法包括在绝缘体上硅衬底的最上侧形成栅极氧化物; 在所述栅极氧化物上形成第一多晶硅层; 以及在所述第一多晶硅层上形成第一二氧化硅层。 然后在第一二氧化硅层上形成第一氮化硅层，接着形成第二二氧化硅层。 通过所有以前的介电层蚀刻浅沟槽并进入SOI衬底。 蚀刻的沟槽用另一介质层（例如二氧化硅）填充并平坦化。 去除每个前述电介质层，留下电介质层的最上面的侧壁区域暴露以与稍后施加的多晶硅栅极区域接触。 侧壁区域的形成确保全场氧化物厚度，从而产生具有减小的电场和栅极和漂移区域之间的减小的电容的器件。

    High-voltage field-effect transistor and method for manufacturing a high-voltage field-effect transistor
    10.
    发明申请
    High-voltage field-effect transistor and method for manufacturing a high-voltage field-effect transistor 失效
    高压场效应晶体管及制造高电压场效应晶体管的方法

    公开(公告)号：US20070262376A1

    公开(公告)日：2007-11-15

    申请号：US11518449

    申请日：2006-09-11

    申请人： Volker Dudek ,  Michael Graf ,  Stefan Schwantes

    发明人： Volker Dudek ,  Michael Graf ,  Stefan Schwantes

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0873 ,  H01L21/266 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66681 ,  H01L29/7824

    摘要： High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type is connected to the body terminal. A body semiconductor region of the second conductivity type, is partially adjacent to the gate oxide to form a channel and is adjacent to the body terminal semiconductor region. A drift semiconductor region of the first conductivity type is adjacent to the drain semiconductor region and the body semiconductor region, wherein in the drift semiconductor region, a potential barrier is formed in a region distanced from the body semiconductor region.

    摘要翻译： 提供了高压场效应晶体管，其包括漏极端子，源极端子，主体端子和栅极端子。 与栅极氧化物相邻的栅极氧化物和栅电极连接到栅极端子。 第一导电类型的漏极半导体区域连接到漏极端子。 第一导电类型的源极半导体区域连接到源极端子。 第二导电类型的主体端子半导体区域连接到主体端子。 第二导电类型的体半导体区域部分地与栅极氧化物相邻以形成沟道并且邻近体终端半导体区域。 第一导电类型的漂移半导体区域与漏极半导体区域和体半导体区域相邻，其中在漂移半导体区域中，在远离体半导体区域的区域中形成势垒。