公开(公告)号：US06255215B1

公开(公告)日：2001-07-03

申请号：US09175652

申请日：1998-10-20

申请人： Fred Hause ,  Charles E. May ,  William S. Brennan

发明人： Fred Hause ,  Charles E. May ,  William S. Brennan

IPC分类号： H01L2144

CPC分类号： H01L21/28518

摘要： A process for forming a silicide layer using a metal layer formed by collimated deposition is provided. The collimated metal layer may, for example, be formed by sputtering metal particles and filtering the metal particles prior to forming the metal layer. By depositing metal in this manner, the resistance of the resultant metal silicide layer can be reduced as compared to metal silicide layers formed using conventional techniques. Lower silicidation reaction temperatures may also be employed.

摘要翻译： 提供了使用通过准直沉积形成的金属层形成硅化物层的工艺。 准直金属层可以例如通过溅射金属颗粒并在形成金属层之前过滤金属颗粒来形成。 通过以这种方式沉积金属，与使用常规技术形成的金属硅化物层相比，所得金属硅化物层的电阻可以降低。 也可以采用较低的硅化反应温度。

公开(公告)号：US08202810B2

公开(公告)日：2012-06-19

申请号：US11971331

申请日：2008-01-09

申请人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

发明人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

IPC分类号： H01L21/31

CPC分类号： H01L21/76877 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76883 ,  Y10S438/902

摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

摘要翻译： 一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化 ，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

公开(公告)号：US06614064B1

公开(公告)日：2003-09-02

申请号：US10060422

申请日：2002-01-30

申请人： Paul R. Besser ,  William S. Brennan

发明人： Paul R. Besser ,  William S. Brennan

IPC分类号： H01L2972

CPC分类号： H01L21/28061 ,  H01L29/4941

摘要： The present invention is generally directed to a transistor having a gate stack comprised of a metal, and a method of making same. In one illustrative embodiment, the transistor is comprised of a gate stack comprised of a gate insulation layer positioned above a semiconducting substrate, a layer of silicon positioned above the gate insulation layer, a layer of adhesion material positioned above the layer of silicon, a layer of metal positioned above the layer of adhesion material, and a plurality of source/drain regions formed in the substrate adjacent the gate stack.

摘要翻译： 本发明一般涉及具有由金属构成的栅极叠层的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括栅极堆叠，栅极堆叠包括位于半导体衬底上方的栅极绝缘层，位于栅极绝缘层上方的硅层，位于硅层之上的粘合材料层， 位于粘合材料层之上的金属，以及形成在邻近栅叠层的衬底中的多个源/漏区。

公开(公告)号：US5894168A

公开(公告)日：1999-04-13

申请号：US947521

申请日：1997-10-02

申请人： Mark W. Michael ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  William S. Brennan

发明人： Mark W. Michael ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  William S. Brennan

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/528 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L23/528 ,  H01L2924/0002

摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

摘要翻译： 提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。 衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化 抛光技术。 所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。 操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。 非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。 因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。 掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

公开(公告)号：US5850105A

公开(公告)日：1998-12-15

申请号：US822120

申请日：1997-03-21

申请人： Robert Dawson ,  Mark W. Michael ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  William S. Brennan

发明人： Robert Dawson ,  Mark W. Michael ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  William S. Brennan

IPC分类号： H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.

摘要翻译： 一种用于形成具有全局平坦化的上表面的多层互连结构的方法。 电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。 随后的化学机械抛光产生基本平坦的表面。

公开(公告)号：US5759913A

公开(公告)日：1998-06-02

申请号：US658547

申请日：1996-06-05

申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L21/768 ,  H01L21/283

CPC分类号： H01L21/7682 ,  H01L21/76828

摘要： A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During deposition, the dielectric is forced along the sidewall of the spaced interconnects as a result of moisture ougasing from the hygroscopic dielectric. Over a period of time, a keyhole occurs with pile up accumulation (or cusping) at the corners of the spaced interconnects. By decreasing the deposition temperature in a subsequent step, outgasing is minimized, and deposition over the keyhole and upon the hygroscopic dielectric takes place. Keyhole coverage results in an air gap which is surrounded on all sides by the fill dielectric. Air gap between interconnects helps reduce permittivity of the overall dielectric structure, resulting in a lessening of the interconnect line-to-line capacitance.

摘要翻译： 提供介电材料，其具有在互连之间的介电沉积期间形成的气隙。 电介质沉积在具有特定纵横比的互连隔开的几何形状中，并且在几何形状的底部暴露于吸湿电介质。 在沉积期间，电介质由于从吸湿介质的湿气渗出而沿着间隔开的互连件的侧壁被迫。 在一段时间内，在间隔互连的角落处堆积积聚（或缩小）时，会产生锁孔。 通过在随后的步骤中降低沉积温度，最大限度地减少了沉积，并且在钥匙孔和吸湿介质上沉积。 钥匙孔覆盖导致气隙由填充电介质所包围。 互连之间的空气间隙有助于降低整个电介质结构的介电常数，导致互连线对线电容的减小。

公开(公告)号：US06514858B1

公开(公告)日：2003-02-04

申请号：US09829202

申请日：2001-04-09

申请人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

发明人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

IPC分类号： H01L214763

CPC分类号： H01L22/34 ,  B24B37/042 ,  B24B49/00 ,  H01L21/31053 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

摘要翻译： 提供了一种用于控制半导体器件的抛光工艺的测试结构。 测试结构由结构层，第一处理层和互连构成。 第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。 多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。 开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。 因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

公开(公告)号：US06376330B1

公开(公告)日：2002-04-23

申请号：US08655242

申请日：1996-06-05

申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L2176

CPC分类号： H01L21/7682

摘要： A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

摘要翻译： 提供一种电介质材料，其具有在电介质中有目的地形成的气隙。 电介质被沉积，并且在相应的互连线之间形成气隙。 有意地控制互连线之间的几何形状以实现在电介质CVD期间产生气隙所需的大的纵横比。 互连之间存在空隙，以减少线间电容，从而减少与紧密间隔的互连相关的传播延迟。

公开(公告)号：US6156650A

公开(公告)日：2000-12-05

申请号：US191576

申请日：1998-11-13

申请人： Tim Z. Hossain ,  William S. Brennan ,  Berta Valdez ,  Renee S. Prusik ,  Amiya R. Ghatak-Roy

发明人： Tim Z. Hossain ,  William S. Brennan ,  Berta Valdez ,  Renee S. Prusik ,  Amiya R. Ghatak-Roy

IPC分类号： H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/32051

摘要： A method of making a semiconductor device to reduce or prevent defects caused by the ejection of deposited material. The method includes a first layer of material deposited over a substrate in the presence of a gaseous ambient. A portion of the gaseous ambient is trapped by the first layer. This entrapped portion could cause defects during subsequent elevated temperature processing as the gas attempts to escape from the first layer. To prevent or reduce this problem, after depositing the first layer and before depositing a second layer over the first layer, the first layer is heated to remove at least a portion of the gaseous ambient trapped in the layer. For best results, the first layer is heated to a temperature at least as high as the highest temperature of later processing steps and at a pressure of no more than 1 torr. This method is particularly useful for layers formed by physical vapor deposition.

摘要翻译： 制造半导体器件以减少或防止由沉积材料的喷射引起的缺陷的方法。 该方法包括在气体环境存在下沉积在衬底上的第一材料层。 气态环境的一部分被第一层捕获。 当气体试图从第一层逸出时，该夹带部分在随后的高温处理期间可能引起缺陷。 为了防止或减少这个问题，在沉积第一层之后并且在第一层上沉积第二层之前，第一层被加热以除去被捕获在该层中的气态环境的至少一部分。 为了获得最佳效果，将第一层加热到至少与后续加工步骤的最高温度一样高的温度，并且在不超过1托的压力下。 该方法对于通过物理气相沉积形成的层特别有用。

公开(公告)号：US6127719A

公开(公告)日：2000-10-03

申请号：US038464

申请日：1998-03-11

申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L21/74 ,  H01L29/00 ,  H01L31/119

CPC分类号： H01L21/74

摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

摘要翻译： 提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。 在形成场电介质之后，将子场导电层置于硅衬底内。 导电层表示驻留在隔离器件之间的掩埋互连。 然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。 埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。