-
公开(公告)号：US09219209B2
公开(公告)日：2015-12-22
申请号：US14112279
申请日：2012-04-25
CPC分类号： H01L33/62 , H01L24/13 , H01L24/14 , H01L33/005 , H01L33/0079 , H01L33/486 , H01L2224/13008 , H01L2224/13022 , H01L2224/13144 , H01L2224/1403 , H01L2224/14051 , H01L2224/16225 , H01L2224/16227 , H01L2224/17517 , H01L2924/01019 , H01L2924/12041 , H01L2924/12042 , H01L2924/181 , H01L2924/351 , H01L2933/0066 , H01L2924/00014 , H01L2924/00
摘要： A light emitting diode (LED) structure (10) has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer (34) is formed in the gap followed by filling the gap with a metal (42). The metal is patterned to form stud bumps (40, 42, 44) that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.
摘要翻译： 发光二极管（LED）结构（10）具有半导体层，包括p型层，有源层和n型层。 p型层具有底面，n型层具有发射光的顶面。 蚀刻p型层和有源层的部分以露出n型层。 LED的表面用光致抗蚀剂图案化，并且铜暴露在暴露的表面上以形成与其各自的半导体层电接触的p和n电极。 n和p电极之间有间隙。 为了在间隙之间提供半导体层的机械支撑，在间隙中形成介电层（34），随后用金属（42）填充间隙。 金属被图案化以形成基本上覆盖LED管芯的底表面但不会使电极短路的螺柱凸块（40,42,44）。 基本均匀的覆盖在后续工艺步骤中支持半导体层。
-
2.发明授权Method of reducing electromigration by forming an electroplated copper-zinc interconnect and a semiconductor device thereby formed 有权通过形成电镀铜 - 锌互连和由此形成的半导体器件来减少电迁移的方法公开(公告)号：US06717236B1
公开(公告)日：2004-04-06
申请号：US10084563
申请日：2002-02-26
IPC分类号： H01L27082
CPC分类号： H01L21/2885 , C25D3/58 , C25D7/123 , C25D17/001 , H01L21/76877
摘要： A method of reducing electromigration in a dual-inlaid copper interconnect line (3) by filling a via (6) with a Cu-rich Cu—Zn alloy (30) electroplated on a Cu surface (200 from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a reduced-oxygen Cu—Zn alloy as fill (30) for the via (6) in forming the dual-inlaid interconnect structure (35). The alloy fill (30) is formed by electroplating the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the fill (30) on the Cu surface (20); and annealing the electroplated Cu—Zn alloy fill (30); and planarizing the Cu—Zn alloy fill (30), thereby forming the dual-inlaid copper interconnect line (35).
摘要翻译： 通过在铜表面（200来自稳定的化学溶液和由稳定的化学溶液以及电解质的方式）电镀Cu富Cu Cu-Zn合金（30）填充通孔（6）来减少双镶嵌铜互连线（3）中的电迁移的方法 控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性，以及由此形成的半导体器件，该方法包括使用还原氧Cu-Zn合金作为通孔（6）的填充物（30），形成双重 所述合金填充物（30）通过以包含Zn和Cu的盐的独特的化学溶液，它们的络合剂，pH调节剂和表面活性剂电镀Cu表面（20）而形成，由此电镀 在Cu表面（20）上填充（30）;对电镀的Cu-Zn合金填料（30）进行退火;以及平坦化Cu-Zn合金填料（30），由此形成双嵌入铜互连线（35）。
-
3.发明授权Method of reducing electromigration in a copper line by Zinc-Doping of a copper surface from an electroplated copper-zinc alloy thin film and a semiconductor device thereby formed 有权通过从电镀铜 - 锌合金薄膜和由此形成的半导体器件的铜表面镀锌来减少铜线中的电迁移的方法公开(公告)号：US06624075B1
公开(公告)日：2003-09-23
申请号：US10288862
申请日：2002-11-05
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu—Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu—Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.
摘要翻译： 一种通过在铜（Cu）表面上电镀铜离子铜（Cu）的中间铜 - 锌合金（Cu-Zn）薄膜上，通过用Zn掺杂Cu表面来限制沿Cu表面的Cu扩散路径来减少铜互连线中的电迁移的方法 稳定的化学溶液，并且控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性，以及由此形成的半导体器件。 该方法包括使用临时还原氧Cu-Zn合金薄膜来形成封装的双镶嵌互连结构。 通过电镀电镀Cu表面，通过电镀Cu晶体，以独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂形成Cu表面; 并对中间电镀Cu-Zn合金薄膜和Cu填充进行退火; 并平坦化互连结构。
-
4.发明授权公开(公告)号：US08202810B2
公开(公告)日：2012-06-19
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/31
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译： 一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化 ，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。
-
5.发明授权Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of copper 有权具有铜填充通孔的半导体器件包括用于减少铜的电迁移的铜 - 锌/合金膜公开(公告)号：US06515368B1
公开(公告)日：2003-02-04
申请号：US10016410
申请日：2001-12-07
IPC分类号： H01L23532
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu—Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu—Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.
摘要翻译： 一种通过在铜（Cu）表面上电镀铜离子铜（Cu）的中间铜 - 锌合金（Cu-Zn）薄膜上，通过用Zn掺杂Cu表面来限制沿Cu表面的Cu扩散路径来减少铜互连线中的电迁移的方法 稳定的化学溶液，并且控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性，以及由此形成的半导体器件。 该方法包括使用临时还原氧Cu-Zn合金薄膜来形成封装的双镶嵌互连结构。 通过电镀电镀Cu表面，通过电镀Cu晶体，以独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂形成Cu表面; 并对中间电镀Cu-Zn合金薄膜和Cu填充进行退火; 并平坦化互连结构。
-
6.发明授权Electrically programmable and erasable memory device and method of fabrication thereof 有权电可编程和可擦除存储器件及其制造方法公开(公告)号：US08633074B2
公开(公告)日：2014-01-21
申请号：US12284002
申请日：2008-09-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
IPC分类号： H01L21/336
CPC分类号： H01L29/7888 , H01L21/28282 , H01L27/11517 , H01L27/11563 , H01L29/513 , H01L29/792
摘要： The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.
摘要翻译： 本存储器件包括衬底，衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的电介质，并且包括氮氧化硅，以及在电介质上的控制栅极。 还提供了一种用于制造这种存储器件的方法，包括用于形成氮氧化硅的各种方法。
-
7.发明申请Electrically programmable and erasable memory device and method of fabrication thereof 有权电可编程和可擦除存储器件及其制造方法公开(公告)号：US20100065901A1
公开(公告)日：2010-03-18
申请号：US12284002
申请日：2008-09-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/7888 , H01L21/28282 , H01L27/11517 , H01L27/11563 , H01L29/513 , H01L29/792
摘要： The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.
摘要翻译： 本存储器件包括衬底，衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的电介质，并且包括氮氧化硅，以及在电介质上的控制栅极。 还提供了一种用于制造这种存储器件的方法，包括用于形成氮氧化硅的各种方法。
-
8.发明申请公开(公告)号：US20090176369A1
公开(公告)日：2009-07-09
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译： 一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化 ，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。
-
9.发明授权Semiconductor device having copper lines with reduced electromigration using an electroplated interim copper-zinc alloy film on a copper surface 失效具有在铜表面上使用电镀的中间铜 - 锌合金膜的具有减少的电迁移的铜线的半导体器件公开(公告)号：US06936925B1
公开(公告)日：2005-08-30
申请号：US10626371
申请日：2003-07-23
IPC分类号： C25D3/58 , C25D5/18 , C25D7/12 , H01L21/288 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76846 , C25D3/58 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要： The present invention relates to the semiconductor device fabrication industry. More particularly a semiconductor device, having an interim reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35). The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.
摘要翻译： 本发明涉及半导体器件制造业。 更具体地说，一种半导体器件，具有通过使用电镀设备电镀Cu，Cu表面（20）上电镀在布置在通孔（6）上的铜箔表面（20）上的临时还原氧Cu-Zn合金薄膜（30） ）在一种独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂; 并对中间电镀Cu-Zn合金薄膜进行退火; 用另外的Cu（26）填充通孔（6）; 退火和平坦化互连结构（35）。 通过降低铜线（35）/通孔（6）中的漂移速度，可以实现铜互连线（35）中电迁移的减少，从而通过使用中间保形来降低铜迁移率以及空隙形成速率 从稳定的化学溶液电镀在Cu表面（20）上的富Cu Cu-Zn合金薄膜（30），并且通过控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性。
-
10.发明授权Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed 有权通过在铜表面上电镀临时铜 - 锌合金薄膜和由此形成的半导体器件来减少铜线中的电迁移的方法公开(公告)号：US06660633B1
公开(公告)日：2003-12-09
申请号：US10083809
申请日：2002-02-26
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , C25D3/58 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , H01L21/76858 , H01L21/76864 , H01L21/76873 , H01L2221/1089
摘要： A method of fabricating a semiconductor device, having an interim reduced-oxygen Cu-Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35); and a semiconductor device thereby formed. The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.
摘要翻译： 一种制造半导体器件的方法，其具有通过使用电镀设备通过电镀设置在通孔（6）中的铜箔表面（20）上电镀的临时还原氧Cu-Zn合金薄膜，所述Cu表面 （20）在独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂; 并对中间电镀Cu-Zn合金薄膜进行退火; 用另外的Cu（26）填充通孔（6）; 退火和平坦化互连结构（35）; 并由此形成半导体器件。 通过降低铜线（35）/通孔（6）中的漂移速度，可以实现铜互连线（35）中电迁移的减少，从而通过使用中间保形来降低铜迁移率以及空隙形成速率 从稳定的化学溶液电镀在Cu表面（20）上的富Cu Cu-Zn合金薄膜（30），并且通过控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性。
-
-
-
-
-
-
-
-
-
搜索结果
16 条记录 (耗时 0.015 秒)
