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1.发明授权Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations 失效在数据寄存器中传播异常状态的方法和系统，以及用非投机操作检测投机操作的异常
公开(公告)号：US5778219A
公开(公告)日：1998-07-07
申请号：US597784
申请日：1996-02-07
申请人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
发明人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3863
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.
摘要翻译： 支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。 如果推测操作使用产生异常的推测操作的结果，则会传播该异常。 使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。 用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。 功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。 要检查延迟异常，功能单元然后读取寄存器文件。 如果检测到异常，则处理异常，并且在需要处理异常的情况下重新执行一个或多个推测操作（以非推测模式）。
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2.发明授权Method and system for deferring exceptions generated during speculative execution 失效用于推迟在投机执行期间产生的异常的方法和系统
公开(公告)号：US5692169A
公开(公告)日：1997-11-25
申请号：US324940
申请日：1994-10-18
申请人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
发明人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/30189 , G06F9/3842
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.
摘要翻译： 支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。 如果推测操作使用产生异常的推测操作的结果，则会传播该异常。 使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。 用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。 功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。 要检查延迟异常，功能单元然后读取寄存器文件。
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3.发明授权Memory processor that prevents errors when load instructions are moved in the execution sequence 失效内存处理器可以在执行顺序中移动加载指令时防止错误
公开(公告)号：US5475823A
公开(公告)日：1995-12-12
申请号：US261647
申请日：1994-06-17
CPC分类号： G06F9/30043 , G06F9/3834
摘要： A memory processor which prevents errors when the compiler advances long latency load instructions in the instruction sequence to reduce the loss of efficiency resulting from the latency time. The memory processor intercepts all load and store instructions prior to the instructions entering the memory pipeline. The memory processor stores load instructions for a period of time sufficient to determine if any subsequent store instruction that would have been executed prior to the load instruction, had the load instruction not been moved, references the same address as that specified in the load instruction. If a store instruction references the load instruction address, the invention returns the same data as the load instruction would have if it was not moved by the compiler.
摘要翻译： 一种存储器处理器，当编译器在指令序列中前进长延迟加载指令时，可以防止错误，以减少延迟时间导致的效率损失。 存储器处理器在指令进入存储器管线之前拦截所有的加载和存储指令。 存储器处理器将加载指令存储一段时间，足以确定在加载指令之前已经执行的加载指令是否有任何后续存储指令，如果加载指令未被移动，则引用与加载指令中指定的地址相同的地址。 如果存储指令引用加载指令地址，则本发明返回与加载指令不被编译器移动的数据相同的数据。
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公开(公告)号：US06581187B2
公开(公告)日：2003-06-17
申请号：US10068723
申请日：2002-02-06
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.
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公开(公告)号：US06385757B1
公开(公告)日：2002-05-07
申请号：US09378395
申请日：1999-08-20
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.
摘要翻译： VLIW处理器设计系统可自动设计可编程和不可编程的VLIW处理器。 系统将输入操作码，操作码的I / O格式，寄存器文件规范以及指令级并行约束作为输入。 通过该输入规范，系统从宏单元数据库构建数据通路，包括功能单元，寄存器文件及其互连组件。 系统使用输入和数据路径生成指令格式设计。 然后可以使用指令格式来构造处理器控制路径。 抽象输入和数据路径可以用于提取适合于将编译器重新定位到处理器的机器描述。 为了优化特定应用程序的处理器，系统根据由重定向编译器生成的应用程序的操作问题统计信息选择自定义指令模板。
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公开(公告)号：US06651222B2
公开(公告)日：2003-11-18
申请号：US10068216
申请日：2002-02-06
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.
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公开(公告)号：US5404484A
公开(公告)日：1995-04-04
申请号：US945561
申请日：1992-09-16
CPC分类号： G06F9/30047 , G06F12/0862 , G06F12/0888 , G06F9/383 , G06F2212/6022 , G06F2212/6028
摘要： The improved cache system reduces the effects of latency times by utilizing a preload instruction inserted by the compiler into the code. The preload instruction is sent sufficiently in advance of the corresponding load instruction to guarantee that the relevant data is in the cache memory when the load instruction is received. In addition, the invention prevents the pollution of the cache with data that will only be used once during the expected lifetime of the data in the cache. This second feature of the invention assures that a large number of references to data that will only be used once does not result in the contents of the cache being replaced with the subsequent need to reload the contents after the data references have been completed.
摘要翻译： 改进的缓存系统通过利用编译器插入到代码中的预加载指令来减少延迟时间的影响。 预加载指令在相应的加载指令之前被充分发送，以便在接收到加载指令时保证相关数据在高速缓冲存储器中。 此外，本发明通过在高速缓存中的数据的期望寿命期间仅使用一次的数据来防止高速缓存的污染。 本发明的第二个特征确保了大量仅仅使用一次的数据的引用不会导致高速缓存的内容被替换为在数据引用完成之后随后需要重新加载内容。
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8.发明授权
公开(公告)号：US5615386A
公开(公告)日：1997-03-25
申请号：US588151
申请日：1996-01-18
申请人： Frederic C. Amerson , Rajiv Gupta , Balasubramanian Kumar , Michael S. Schlansker , William S. Worley
发明人： Frederic C. Amerson , Rajiv Gupta , Balasubramanian Kumar , Michael S. Schlansker , William S. Worley
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3844
摘要： An improved data processing system for executing branch instructions which has lower latency times and which only rarely requires the instruction pipeline to be flushed is disclosed. The data processing system utilizes a register file to hold the information needed to execute a branch instruction. The information is loaded into the register file in advance of the branch instruction. This allows the system to prepare more than one branch instruction at any given time. The present invention may be used to cause the cache line containing the target address of the branch instruction to be loaded soon as the target address is available for the branch instruction. Since the outcome of the branch instruction is almost always known when the branch instruction enters the instruction pipeline, the instruction pipeline only rarely needs to be flushed.
摘要翻译： 公开了一种用于执行具有较低等待时间并且很少需要刷新指令流水线的分支指令的改进的数据处理系统。 数据处理系统利用寄存器文件来保存执行分支指令所需的信息。 信息在分支指令之前被加载到寄存器文件中。 这允许系统在任何给定时间准备多个分支指令。 本发明可以用于使得包含分支指令的目标地址的高速缓存线在目标地址对于分支指令可用时很快被加载。 由于分支指令的结果在分支指令进入指令流水线时几乎总是被知道，所以指令流水线很少需要刷新。
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9.发明授权Method and apparatus for enabling a computer system to adjust for latency assumptions 失效使计算机系统能够调整等待时间假设的方法和装置
公开(公告)号：US5710912A
公开(公告)日：1998-01-20
申请号：US059041
申请日：1993-05-06
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3869
摘要： A method and system are disclosed which allow a computer program to execute properly in object code compatible processing systems which have latencies different from those with which the program was created or compiled. This resulting compatibility of the computer program is achieved because the invention protects the precedence of operations within the computer program using latency assumptions which were used when creating the computer program. When the computer program is created, latency assumption information is efficiently provided within the computer program. Thereafter, when the computer program is executed, it is able to advise the processing system of the latency assumptions with which it was created. Various ways are described in which the processing system can utilize the latency assumptions when executing the computer program so as to ensure compatibility.
摘要翻译： 公开了一种方法和系统，其允许计算机程序在目标代码兼容的处理系统中正确地执行，该处理系统的延迟与程序被创建或编译的时间不同。 实现计算机程序的这种兼容性是因为本发明使用在创建计算机程序时使用的延迟假设来保护计算机程序内的操作的优先级。 当创建计算机程序时，计算机程序内有效地提供延迟假设信息。 此后，当执行计算机程序时，能够向处理系统通知其创建的延迟假设。 描述了各种方式，其中处理系统可以在执行计算机程序时利用延迟假设，以确保兼容性。
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10.发明授权Automated design of processor systems using feedback from internal measurements of candidate systems 失效使用候选系统内部测量的反馈自动设计处理器系统公开(公告)号：US06408428B1
公开(公告)日：2002-06-18
申请号：US09378290
申请日：1999-08-20
申请人： Michael S. Schlansker , Vinod K. Kathail , Greg Snider , Shail Aditya Gupta , Scott A. Mahlke , Santosh Abraham
发明人： Michael S. Schlansker , Vinod K. Kathail , Greg Snider , Shail Aditya Gupta , Scott A. Mahlke , Santosh Abraham
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/08
摘要： An automated design system for VLIW processors explores a parameterized design space to assist in identifying candidate processor designs that satisfy desired design constraints, such as processor cost and performance. A VLIW synthesis process takes as input a specification of processor parameters and synthesizes a datapath specification, an instruction format design, and a control path specification. The synthesis process also extracts a machine description suitable to re-target a compiler. The re-targeted compiler generates operation issue statistics for an application program or set of programs. Using these statistics, a procedure for searching the design space can extract internal resources utilization information that is used to determine new candidate processors for evaluation.
摘要翻译： 用于VLIW处理器的自动化设计系统探索参数化设计空间，以帮助识别满足期望设计约束（例如处理器成本和性能）的候选处理器设计。 VLIW合成过程将处理器参数的规范作为输入，并合成数据路径规范，指令格式设计和控制路径规范。 合成过程还提取适合于重新定位编译器的机器描述。 重新定位的编译器生成应用程序或程序集的操作问题统计信息。 使用这些统计信息，搜索设计空间的过程可以提取用于确定新的候选处理器进行评估的内部资源利用率信息。
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