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    Clock and data recovery method and digital circuit for the same
    1.
    发明授权
    Clock and data recovery method and digital circuit for the same 失效
    时钟和数据恢复方法与数字电路相同

    公开(公告)号：US07474720B2

    公开(公告)日：2009-01-06

    申请号：US10722484

    申请日：2003-11-28

    申请人： Fumio Yuuki ,  Hiroki Yamashita ,  Masahito Sonehara

    发明人： Fumio Yuuki ,  Hiroki Yamashita ,  Masahito Sonehara

    IPC分类号： H04L7/00 ,  H04J3/06

    CPC分类号： H04L7/0331 ,  H03L7/0814 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0337

    摘要： A clock data recovery circuit has a good jitter tolerance characteristic and a broad data recovery range in the event of a wander, that is, a good wander-tracking characteristic of a recovered clock signal. The clock data recovery circuit executes control to compare the position of the edge of data with the position of the edge of a data recovery clock signal (a recovered clock signal) and keeps the clock edge away from the data edge if a gap between the edges becomes smaller than a reference value. A cycle of a reference clock signal is divided into N portions to generate N clock signals (pl ) with phases different from each other in composition circuits. By executing control to turn on 2 of the N selector control signals supplied to each 2 adjacent pins of the N−1 selectors at the same time, the N−1 selectors are capable of generating a middle phase between first and second phases and, hence, generating one of N×2 phases from N input phases as the phase of the data recovery clock signal.

    摘要翻译： 时钟数据恢复电路在漂移的情况下具有良好的抖动容限特性和广泛的数据恢复范围，即，恢复的时钟信号的漂移跟踪特性良好。 时钟数据恢复电路执行控制以将数据边缘的位置与数据恢复时钟信号（恢复的时钟信号）的边沿的位置进行比较，并且如果边缘之间的间隙保持时钟边缘远离数据边缘 变得小于参考值。 参考时钟信号的周期被分成N个部分，以在合成电路中产生具有彼此不同的相位的N个时钟信号（pl）。 通过执行控制以同时接通提供给N-1个选择器的每个2个相邻引脚的N个选择器控制信号中的2个，N-1选择器能够在第一和第二相之间产生中间相位，因此 从N个输入相位产生Nx2相位之一作为数据恢复时钟信号的相位。

    Logic circuit
    2.
    发明授权
    Logic circuit 失效
    逻辑电路

    公开(公告)号：US07034568B2

    公开(公告)日：2006-04-25

    申请号：US10886035

    申请日：2004-07-08

    申请人： Hiroki Yamashita ,  Akio Koyama ,  Tatsuhiro Aida ,  Atsushi Itoh ,  Masahito Sonehara

    发明人： Hiroki Yamashita ,  Akio Koyama ,  Tatsuhiro Aida ,  Atsushi Itoh ,  Masahito Sonehara

    IPC分类号： H03K17/16

    CPC分类号： H03K19/00369 ,  H03F1/301 ,  H03K19/09448

    摘要： The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage. The reference-voltage generating circuit 119 comprises an n-type MOS transistor 111, a bipolar transistor 112 which determines the drain voltage of the n-type MOS transistor 111, and a control circuit 120 for controlling the drain current of the n-type MOS transistor 111.

    摘要翻译： 电流源电流的电源电压依赖性降低，电源电压降低。 本发明包括发射极耦合逻辑电路118和参考电压产生电路119，用于产生用于控制恒流电源n型MOS晶体管110的漏极电流（=电流源电流ICS）的参考电压VCSC。 发射极耦合逻辑电路118包括由一对发射极耦合双极晶体管106和107构成的电流开关，与电流开关串联连接的恒流供应n型MOS晶体管110和电阻器装置108 和109分别与双极晶体管106和107串联连接以获得输出电压。 参考电压产生电路119包括n型MOS晶体管111，确定n型MOS晶体管111的漏极电压的双极晶体管112和用于控制n型MOS晶体管111的漏极电流的控制电路120 晶体管111。

    Logic circuit
    3.
    发明申请
    Logic circuit 失效
    逻辑电路

    公开(公告)号：US20050068066A1

    公开(公告)日：2005-03-31

    申请号：US10886035

    申请日：2004-07-08

    申请人： Hiroki Yamashita ,  Akio Koyama ,  Tatsuhiro Aida ,  Atsushi Itoh ,  Masahito Sonehara

    发明人： Hiroki Yamashita ,  Akio Koyama ,  Tatsuhiro Aida ,  Atsushi Itoh ,  Masahito Sonehara

    IPC分类号： H03K19/086 ,  H03F1/30 ,  H03F3/45 ,  H03K5/22 ,  H03K19/003 ,  H03K19/0944

    CPC分类号： H03K19/00369 ,  H03F1/301 ,  H03K19/09448

    摘要： The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage. The reference-voltage generating circuit 119 comprises an n-type MOS transistor 111, a bipolar transistor 112 which determines the drain voltage of the n-type MOS transistor 111, and a control circuit 120 for controlling the drain current of the n-type MOS transistor 111.

    摘要翻译： 电流源电流的电源电压依赖性降低，电源电压降低。 本发明包括发射极耦合逻辑电路118和参考电压产生电路119，用于产生用于控制恒流电源n型MOS晶体管110的漏极电流（=电流源电流ICS）的参考电压VCSC。 发射极耦合逻辑电路118包括由一对发射极耦合双极晶体管106和107构成的电流开关，与电流开关串联连接的恒流供应n型MOS晶体管110和电阻器装置108 和109分别与双极晶体管106和107串联连接以获得输出电压。 参考电压产生电路119包括n型MOS晶体管111，确定n型MOS晶体管111的漏极电压的双极晶体管112和用于控制n型MOS晶体管111的漏极电流的控制电路120 晶体管111。

    Analog switch
    4.
    发明授权
    Analog switch 有权
    模拟开关

    公开(公告)号：US08008963B2

    公开(公告)日：2011-08-30

    申请号：US12128637

    申请日：2008-05-29

    申请人： Masahito Sonehara ,  Yoichiro Kobayashi

    发明人： Masahito Sonehara ,  Yoichiro Kobayashi

    IPC分类号： H03K17/687

    CPC分类号： H03K17/04163 ,  H01L2924/0002 ,  H03K17/04206 ,  H01L2924/00

    摘要： An analog switch having a low capacitance is achieved. Potentials of input/output terminals of the analog switch and a well potential and a gate potential of an NMOS switching device are operated in synchronization via level shift buffers, thereby cancelling parasitic capacitances present between these elements.

    摘要翻译： 实现了具有低电容的模拟开关。 模拟开关的输入/输出端子的电位和NMOS开关器件的阱电位和栅极电位通过电平移位缓冲器同步操作，从而消除这些元件之间存在的寄生电容。

    ANALOG SWITCH
    7.
    发明申请
    ANALOG SWITCH 有权
    模拟开关

    公开(公告)号：US20080296685A1

    公开(公告)日：2008-12-04

    申请号：US12128637

    申请日：2008-05-29

    申请人： Masahito Sonehara ,  Yoichiro Kobayashi

    发明人： Masahito Sonehara ,  Yoichiro Kobayashi

    IPC分类号： H01L23/62

    CPC分类号： H03K17/04163 ,  H01L2924/0002 ,  H03K17/04206 ,  H01L2924/00

    摘要： An analog switch having a low capacitance is achieved. Potentials of input/output terminals of the analog switch and a well potential and a gate potential of an NMOS switching device are operated in synchronization via level shift buffers, thereby cancelling parasitic capacitances present between these elements.

    摘要翻译： 实现了具有低电容的模拟开关。 模拟开关的输入/输出端子的电位和NMOS开关器件的阱电位和栅极电位通过电平移位缓冲器同步操作，从而消除这些元件之间存在的寄生电容。