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公开(公告)号：US20070269338A1
公开(公告)日：2007-11-22
申请号：US11632720
申请日：2005-06-27
申请人： Fumitaka Kume , Tomosuke Yoshida , Ken Aihara , Ryoji Hoshi , Satoshi Tobe , Naohisa Toda , Fumio Tahara
发明人： Fumitaka Kume , Tomosuke Yoshida , Ken Aihara , Ryoji Hoshi , Satoshi Tobe , Naohisa Toda , Fumio Tahara
CPC分类号： H01L21/3225 , C30B25/20 , C30B29/06 , C30B33/02 , H01L21/02381 , H01L21/02532
摘要： A silicon epitaxial wafer 100 is formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by means of a CZ method, and doped with boron so that a resistivity thereof is less than 0.018 Ω·cm. The silicon single crystal substrate 1 has a density of bulk stacking faults 13 in the silicon single crystal substrate 1 in the range of 1×108 cm−3 or higher and 3×109 cm−3 or lower. Thereby, provided is a silicon epitaxial wafer having a boron doped p+ CZ substrate with a resistivity of 0.018Ω·cm or lower, and a state of formation of oxygen precipitates can be adjusted adequately so as to secure a sufficient IG effect and to suppress a problem of bow and deformation of a substrate, despite that sizes of oxygen precipitates is so small to be observed accurately.
摘要翻译： 通过在Si单晶衬底1上生长硅外延层2，通过CZ法生长并掺杂硼，使其电阻率小于0.018Ω·cm，形成硅外延晶片100。 硅单晶衬底1在硅单晶衬底1中的体积堆垛层错密度为1×10 -3 -3以上且3×10 6 > 9 -3 或更低。 因此，提供具有电阻率为0.018Omega.cm以下的具有硼掺杂的P + CZ基板的硅外延晶片，并且可以适当地调节氧沉淀物的形成状态，以便确保 足够的IG效应并且抑制基板的弯曲和变形的问题，尽管氧沉淀物的尺寸如此小以被准确地观察。
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公开(公告)号：US07713851B2
公开(公告)日：2010-05-11
申请号：US11660764
申请日：2005-08-03
申请人： Fumitaka Kume , Tomosuke Yoshida , Ken Aihara , Ryoji Hoshi , Satoshi Tobe , Naohisa Toda , Fumio Tahara
发明人： Fumitaka Kume , Tomosuke Yoshida , Ken Aihara , Ryoji Hoshi , Satoshi Tobe , Naohisa Toda , Fumio Tahara
IPC分类号： H01L21/20
CPC分类号： H01L21/02052 , H01L21/3225
摘要： A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 Ω·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
摘要翻译： 在由Czochralski法制造的硅单晶衬底1上以气相生长硅外延层2，并用硼掺杂以将电阻率调节至0.02＆OHgr·cm或更低，氧沉淀核11形成在 硅单晶衬底1，通过在氧化气氛中在450℃至750℃进行退火，持续时间允许在硅上形成仅2nm或更小的氧化硅膜 作为退火的结果的外延层2，使用清洗液，将低温退火后的第一次清洗作为第一清洗来蚀刻所形成的氧化硅膜3。 通过该方法，氧化硅膜的最终剩余厚度可以仅被抑制到与天然氧化膜相当的水平，而不依赖于氢氟酸清洗。
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公开(公告)号：US20070243699A1
公开(公告)日：2007-10-18
申请号：US11660764
申请日：2005-08-03
申请人： Fumitaka Kume , Tomosuke Yoshida , Ken Aihara , Ryoji Hoshi , Satoshi Tobe , Naohisa Toda , Fumio Tahara
发明人： Fumitaka Kume , Tomosuke Yoshida , Ken Aihara , Ryoji Hoshi , Satoshi Tobe , Naohisa Toda , Fumio Tahara
IPC分类号： H01L21/20
CPC分类号： H01L21/02052 , H01L21/3225
摘要： A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 Ω·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.
摘要翻译： 在由Czochralski法制造的硅单晶衬底1上以气相生长硅外延层2，并掺杂硼以将电阻率调节至0.02Ω·cm以下，在硅中形成氧沉淀核11 单晶衬底1，通过在氧化气氛中在450℃至750℃下进行退火，持续时间允许在硅外延上形成仅2nm或更小的氧化硅膜 层2作为退火的结果，并且使用清洁溶液，在低温退火之后，将由此形成的氧化硅膜3作为第一清洗进行蚀刻。 通过该方法，氧化硅膜的最终剩余厚度可以仅被抑制到与天然氧化膜相当的水平，而不依赖于氢氟酸清洗。
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公开(公告)号：US20080038526A1
公开(公告)日：2008-02-14
申请号：US11632719
申请日：2005-07-05
申请人： Fumitaka Kume , Tomosuke Yushida , Ken Aihara , Ryoji Hoshi , Satoshi Tobe , Naohisa Toda , Fumio Tahara
发明人： Fumitaka Kume , Tomosuke Yushida , Ken Aihara , Ryoji Hoshi , Satoshi Tobe , Naohisa Toda , Fumio Tahara
CPC分类号： H01L21/3225 , C30B25/20 , C30B29/06 , C30B33/02 , Y10T428/24992
摘要： A silicon epitaxial wafer 100 formed by growing a silicon epitaxial layer 2 on a silicon single crystal substrate 1, produced by a CZ method, and doped with boron so that a resistivity thereof is in the range of 0.009 Ω·cm or higher and 0.012 Ω·cm or lower. The silicon single crystal substrate 1 has a density of the oxygen precipitation nuclei of 1×1010 cm−3 or higher. A width of a no-oxygen-precipitation-nucleus-forming-region 15, formed between the silicon epitaxial layer 2 and the silicon single substrate 1, is in the range of more than 0 μm and less than 10 μm. Thereby, provided is a silicon epitaxial wafer using a boron doped p+ CZ substrate, wherein a formed width of no-oxygen-precipitation-nucleus-forming-region is reduced sufficiently, and oxygen precipitates can be formed having a density sufficient enough to exert an IG effect.
摘要翻译： 通过在硅单晶衬底1上生长硅外延层2而形成的硅外延晶片100，其通过CZ方法制造并掺杂硼，使其电阻率在0.009Ω.cm以上且0.012Ω .cm或更低。 硅单晶衬底1的氧沉淀核的密度为1×10 10 -3 -3以上。 在硅外延层2和硅单基板1之间形成的无氧析出核形成区域15的宽度在大于0μm且小于10μm的范围内。 由此，提供了使用硼掺杂的P + CZ衬底的硅外延晶片，其中形成的无氧沉淀 - 核形成区域的宽度被充分降低，并且可以形成氧沉淀 具有足以施加IG效应的密度。
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公开(公告)号：US08916953B2
公开(公告)日：2014-12-23
申请号：US13993810
申请日：2012-01-06
申请人： Wei Feng Qu , Fumio Tahara , Yuuki Ooi , Shu Sugisawa
发明人： Wei Feng Qu , Fumio Tahara , Yuuki Ooi , Shu Sugisawa
摘要： The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.
摘要翻译： 本发明提供了一种制造硅单晶晶片的方法，其中对于氧浓度小于7ppma，氮浓度为1×1013至1×1014原子/厘米2的硅单晶晶片进行热处理， cm3，其是通过Czochralski法生长的V型硅单晶锭，在非氮化气氛中在1150〜1300℃下反应1〜120分钟。 结果，制造低成本硅单晶晶片的方法可以通过使用通过CZ方法制造的V区晶片适用于IGBT，该V型晶片可以通过制造大量具有直径增加的方式 没有缺陷并且通过提供径向电阻率分布，其基本上等于实施中子辐射时的径向电阻率分布，而不执行中子照射。
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公开(公告)号：US08900971B2
公开(公告)日：2014-12-02
申请号：US13978840
申请日：2012-01-06
申请人： Tsuyoshi Ohtsuki , Wei Feng Qu , Fumio Tahara , Yuuki Ooi , Kyoko Mitani
发明人： Tsuyoshi Ohtsuki , Wei Feng Qu , Fumio Tahara , Yuuki Ooi , Kiyoshi Mitani
IPC分类号： H01L21/30 , H01L23/00 , H01L21/762 , H01L21/84
CPC分类号： H01L24/83 , H01L21/76254 , H01L21/76256 , H01L21/84 , H01L24/26 , H01L2224/83 , H01L2924/1461 , H01L2924/15788 , H01L2924/00
摘要： The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.
摘要翻译： 本发明提供了一种通过绝缘膜将基底与基片接合而制造键合衬底的方法，包括：多孔层形成步骤，部分地形成多孔层或形成厚度在接合表面上部分变化的多孔层 的基底; 绝缘膜形成步骤，将多孔层改变为绝缘膜，从而形成厚度在基底基板的接合表面上部分变化的绝缘膜; 键合步骤，通过所述绝缘膜将所述基底衬底接合到所述接合衬底; 以及降低键合键合衬底的膜厚以形成薄膜层的膜厚减小步骤。 结果，提供了一种能够通过简单的方法获得其厚度部分变化的绝缘膜的接合基板的制造方法。
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公开(公告)号：US20130341763A1
公开(公告)日：2013-12-26
申请号：US13978840
申请日：2012-01-06
申请人： Yuuki Ooi , Wei Feng Qu , Tsuyoshi Ohtsuki , Kyoko Mitani , Fumio Tahara
发明人： Tsuyoshi Ohtsuki , Wei Feng Qu , Fumio Tahara , Yuuki Ooi , Kiyoshi Mitani
IPC分类号： H01L23/00
CPC分类号： H01L24/83 , H01L21/76254 , H01L21/76256 , H01L21/84 , H01L24/26 , H01L2224/83 , H01L2924/1461 , H01L2924/15788 , H01L2924/00
摘要： The invention provides a method for manufacturing a bonded substrate by bonding a base substrate to a bond substrate through an insulator film, including: a porous layer forming step of partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; an insulator film forming step of changing the porous layer into the insulator film, and thereby forming the insulator film whose thickness partially varies on the bonding surface of the base substrate; a bonding step of bonding the base substrate to the bond substrate through the insulator film; and a film thickness reducing step of reducing a film thickness of the bonded bond substrate to form a thin-film layer. As a result, there is provided the method for manufacturing a bonded substrate that enables obtaining an insulator film whose thickness partially varies with use of a simple method.
摘要翻译： 本发明提供了一种通过绝缘膜将基底与基片接合而制造键合衬底的方法，包括：多孔层形成步骤，部分地形成多孔层或形成厚度在接合表面上部分变化的多孔层 的基底; 绝缘膜形成步骤，将多孔层改变为绝缘膜，从而形成厚度在基底基板的接合表面上部分变化的绝缘膜; 键合步骤，通过所述绝缘膜将所述基底衬底接合到所述接合衬底; 以及降低键合键合衬底的膜厚以形成薄膜层的膜厚减小步骤。 结果，提供了一种能够通过简单的方法获得其厚度部分变化的绝缘膜的接合基板的制造方法。
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8.发明授权Method for evaluating oxide dielectric breakdown voltage of a silicon single crystal wafer 有权评估硅单晶晶片的氧化物绝缘击穿电压的方法公开(公告)号：US08551246B2
公开(公告)日：2013-10-08
申请号：US12990038
申请日：2009-05-07
IPC分类号： C30B15/20
CPC分类号： C30B29/06 , C30B33/02 , H01L21/02008 , H01L22/12 , H01L2924/0002 , Y10T428/24355 , H01L2924/00
摘要： A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
摘要翻译： 一种制造硅单晶晶片的方法，至少具有：制备硅单晶锭的步骤; 切割硅单晶锭以制造多个切片基板的步骤; 通过进行研磨，蚀刻和研磨中的至少一种来将多个切片基板加工成多个基板的处理步骤; 从所述多个基板中取样至少一个的步骤; 通过AFM测量在采样步骤中采样的基板的表面粗糙度并获得对应于20nm至50nm的波长的频带的振幅（强度）以判定接受的步骤; 以及如果判断结果为拒绝则判断结果为接受或执行再处理的步骤，将基板发送到下一步骤。
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公开(公告)号：US20130264685A1
公开(公告)日：2013-10-10
申请号：US13993810
申请日：2012-01-06
申请人： Wei Feng Qu , Fumio Tahara , Yuuki Ooi , Shu Sugisawa
发明人： Wei Feng Qu , Fumio Tahara , Yuuki Ooi , Shu Sugisawa
摘要： The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.
摘要翻译： 本发明提供了一种制造硅单晶晶片的方法，其中对于氧浓度小于7ppma，氮浓度为1×1013至1×1014原子/厘米2的硅单晶晶片进行热处理， cm3，其是通过Czochralski法生长的V型硅单晶锭，在非氮化气氛中在1150〜1300℃下反应1〜120分钟。 结果，制造低成本硅单晶晶片的方法可以通过使用通过CZ方法制造的V区晶片适用于IGBT，该V型晶片可以通过制造大量具有直径增加的方式 没有缺陷并且通过提供径向电阻率分布，其基本上等于实施中子辐射时的径向电阻率分布，而不执行中子照射。
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10.发明申请公开(公告)号：US20110045246A1
公开(公告)日：2011-02-24
申请号：US12990038
申请日：2009-05-07
CPC分类号： C30B29/06 , C30B33/02 , H01L21/02008 , H01L22/12 , H01L2924/0002 , Y10T428/24355 , H01L2924/00
摘要： A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
摘要翻译： 一种制造硅单晶晶片的方法，至少具有：制备硅单晶锭的步骤; 切割硅单晶锭以制造多个切片基板的步骤; 通过进行研磨，蚀刻和研磨中的至少一种来将多个切片基板加工成多个基板的处理步骤; 从所述多个基板中取样至少一个的步骤; 通过AFM测量在采样步骤中采样的基板的表面粗糙度并获得对应于20nm至50nm的波长的频带的振幅（强度）以判定接受的步骤; 以及如果判断结果为拒绝则判断结果为接受或执行再处理的步骤，将基板发送到下一步骤。
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