-
公开(公告)号：US10419501B2
公开(公告)日：2019-09-17
申请号：US14958773
申请日：2015-12-03
Applicant: Futurewei Technologies, Inc.
Inventor： Ashish Rai Shrivastava , Alan Gatherer , Sushma Wokhlu
Abstract: A data streaming unit (DSU) and a method for operating a DSU are disclosed. In an embodiment the DSU includes a memory interface configured to be connected to a storage unit, a compute engine interface configured to be connected to a compute engine (CE) and an address generator configured to manage address data representing address locations in the storage unit. The data streaming unit further includes a data organization unit configured to access data in the storage unit and to reorganize the data to be forwarded to the compute engine, wherein the memory interface is communicatively connected to the address generator and the data organization unit, wherein the address generator is communicatively connected to the data organization unit, and wherein the data organization unit is communicatively connected to the compute engine interface.
-
公开(公告)号：US09983995B2
公开(公告)日：2018-05-29
申请号：US15131779
申请日：2016-04-18
Applicant: Futurewei Technologies, Inc.
Inventor： Sushma Wokhlu , Alan Gatherer , Ashish Rai Shrivastava
IPC: G06F12/00 , G06F12/0831 , G06F12/0877 , G06F12/0893
CPC classification number: G06F12/0893 , G06F12/0877
Abstract: A cache and a method for operating a cache are disclosed. In an embodiment, the cache includes a cache controller, data cache and a delay write through cache (DWTC), wherein the data cache is separate and distinct from the DWTC, wherein cacheable write accesses are split into shareable cacheable write accesses and non-shareable cacheable write accesses, wherein the cacheable shareable write accesses are allocated only to the DWTC, and wherein the non-shareable cacheable write accesses are not allocated to the DWTC.
-
公开(公告)号：US20170169034A1
公开(公告)日：2017-06-15
申请号：US15365755
申请日：2016-11-30
Applicant: Futurewei Technologies, Inc.
Inventor： Ashish Rai Shrivastava , Alex Elisa Chandra , Mark Brown , Debashis Bhattacharya , Alan Gatherer
IPC: G06F17/30
CPC classification number: G06F16/252 , G06F16/211 , G06F16/283
Abstract: A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.
-
公开(公告)号：US10817528B2
公开(公告)日：2020-10-27
申请号：US15365755
申请日：2016-11-30
Applicant: Futurewei Technologies, Inc.
Inventor： Ashish Rai Shrivastava , Alex Elisa Chandra , Mark Brown , Debashis Bhattacharya , Alan Gatherer
Abstract: A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.
-
公开(公告)号：US10691463B2
公开(公告)日：2020-06-23
申请号：US15220067
申请日：2016-07-26
Applicant: Futurewei Technologies, Inc.
Inventor： Sushma Wokhlu , Alan Gatherer , Ashish Rai Shrivastava
Abstract: A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.
-
Patent Agency Ranking
公开(公告)号：US20170300414A1
公开(公告)日：2017-10-19
申请号：US15131779
申请日：2016-04-18
Applicant: Futurewei Technologies, Inc.
Inventor： Sushma Wokhlu , Alan Gatherer , Ashish Rai Shrivastava
IPC: G06F12/08
CPC classification number: G06F12/0893 , G06F12/0877
Abstract: A cache and a method for operating a cache are disclosed. In an embodiment, the cache includes a cache controller, data cache and a delay write through cache (DWTC), wherein the data cache is separate and distinct from the DWTC, wherein cacheable write accesses are split into shareable cacheable write accesses and non-shareable cacheable write accesses, wherein the cacheable shareable write accesses are allocated only to the DWTC, and wherein the non-shareable cacheable write accesses are not allocated to the DWTC.
-
公开(公告)号：US11334355B2
公开(公告)日：2022-05-17
申请号：US15586937
申请日：2017-05-04
Applicant: Futurewei Technologies, Inc.
Inventor： Alan Gatherer , Sushma Wokhlu , Peter Yan , Ywhpyng Harn , Ashish Rai Shrivastava , Tong Sun , Lee Dobson McFearin
IPC: G06F9/38 , G06F9/30 , G06F13/16 , G06F12/0853 , G06F9/46 , G06F12/0884 , G06F3/06 , G06F12/0868 , G06F12/0855
Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.
-
公开(公告)号：US20170168792A1
公开(公告)日：2017-06-15
申请号：US15378714
申请日：2016-12-14
Applicant: Futurewei Technologies, Inc.
Inventor： Debashis Bhattacharya , Alan Gatherer , Mark Brown , Lee Dobson McFearin , Alex Elisa Chandra , Ashish Rai Shrivastava
IPC: G06F9/45
CPC classification number: G06F8/51
Abstract: A method includes obtaining, by a first processor, a first software architecture description file and obtaining, by the first processor, a platform independent model file. The method also includes obtaining, by the first processor, a platform architecture definition file and performing, by the first processor, a first source-to-source compilation in accordance with the first software architecture description file, the platform independent model file, and the platform architecture definition file, to produce generated interface code. Additionally, the method includes generating, by the first processor, run time code, in accordance with the generated interface code and running, by a second processor in real time, the run time code.
-
公开(公告)号：US20160103707A1
公开(公告)日：2016-04-14
申请号：US14877155
申请日：2015-10-07
Applicant: Futurewei Technologies, Inc.
Inventor： Debashis Bhattacharya , Alan Gatherer , Ashish Rai Shrivastava , Mark Brown , Zhenguo Gu , Qiang Wang , Alex Elisa Chandra
CPC classification number: G06F9/4881 , G06F9/44505
Abstract: A method includes receiving, by a system on a chip (SoC) from a logically centralized controller, configuration information and reading, from a semantics aware storage module of the SoC, a data block in accordance with the configuration information. The method also includes performing scheduling to produce a schedule in accordance with the configuration information and writing the data block to an input data queue in accordance with the schedule to produce a stored data block. Additionally, the method includes writing a tag to an input tag queue to produce a stored tag, where the tag corresponds to the data block.
Abstract translation: 一种方法包括：通过来自逻辑中央控制器的芯片上的系统（SoC）从SoC的语义感知存储模块接收配置信息和根据配置信息读取数据块。 该方法还包括执行调度以根据配置信息产生调度，并且根据调度将数据块写入输入数据队列以产生存储的数据块。 此外，该方法包括将标签写入输入标签队列以产生存储的标签，其中标签对应于数据块。
-
公开(公告)号：US10884756B2
公开(公告)日：2021-01-05
申请号：US16876995
申请日：2020-05-18
Applicant: Futurewei Technologies, Inc.
Inventor： Sushma Wokhlu , Alan Gatherer , Ashish Rai Shrivastava
Abstract: A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.013 seconds)
