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公开(公告)号：US10783160B2
公开(公告)日：2020-09-22
申请号：US15264095
申请日：2016-09-13
Applicant: Futurewei Technologies, Inc.
Inventor： Debashis Bhattacharya , Alan Gatherer , Alex Elisa Chandra , Mark Brown , Hao Luan , Ashish Rai Shrivastava
Abstract: A computation system-on-a-chip (CSoC) includes a first scalable distributed real-time Data Warehousing (sdrDW) engine and a network interface coupled to the first sdrDW engine, where the network interface is coupled to an interconnect, and where the CSoC is configured to transmit a task request over the interconnect to a first networked bulk storage controller (NBSC) requesting that a task be performed on a bulk storage medium.
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公开(公告)号：US20170293586A1
公开(公告)日：2017-10-12
申请号：US15097091
申请日：2016-04-12
Applicant: Futurewei Technologies, Inc.
Inventor： Peter Yan , Alex Elisa Chandra , Lee Dobson McFearin , Fang Yu , Alan Gatherer
CPC classification number: G06F13/4221 , G06F13/20 , G06F15/7825
Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
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公开(公告)号：US10387355B2
公开(公告)日：2019-08-20
申请号：US15097091
申请日：2016-04-12
Applicant: Futurewei Technologies, Inc.
Inventor： Peter Yan , Alex Elisa Chandra , Lee Dobson McFearin , Fang Yu , Alan Gatherer
Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
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公开(公告)号：US20170169034A1
公开(公告)日：2017-06-15
申请号：US15365755
申请日：2016-11-30
Applicant: Futurewei Technologies, Inc.
Inventor： Ashish Rai Shrivastava , Alex Elisa Chandra , Mark Brown , Debashis Bhattacharya , Alan Gatherer
IPC: G06F17/30
CPC classification number: G06F16/252 , G06F16/211 , G06F16/283
Abstract: A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.
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公开(公告)号：US10185606B2
公开(公告)日：2019-01-22
申请号：US15096966
申请日：2016-04-12
Applicant: Futurewei Technologies, Inc.
Inventor： Peter Yan , Alan Gatherer , Alex Elisa Chandra , Lee Dobson Mcfearin , Mark Brown , Debashis Bhattacharya , Fang Yu , Xingfeng Chen , Yan Bei , Ke Ning , Chushun Huang , Tong Sun , Xiaotao Chen
Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
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Patent Agency Ranking
公开(公告)号：US20170103093A1
公开(公告)日：2017-04-13
申请号：US15169094
申请日：2016-05-31
Applicant: Futurewei Technologies, Inc.
Inventor： Alex Elisa Chandra , Mark Brown , Debashis Bhattacharya , Alan Gatherer
IPC: G06F17/30
CPC classification number: G06F16/2219 , G06F16/245 , G06F16/2455 , G06F16/25
Abstract: A method includes receiving, by a real-time Data Warehouse (rDW) from a first task, a first dataset and spreading the first dataset to produce a first plurality of objects, where the first plurality of objects includes a first object and a second object. The method also includes storing the first object in a first location in an rDW data repository and storing the second object in a second location in the rDW data repository.
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公开(公告)号：US20170103076A1
公开(公告)日：2017-04-13
申请号：US15264095
申请日：2016-09-13
Applicant: Futurewei Technologies, Inc.
Inventor： Debashis Bhattacharya , Alan Gatherer , Alex Elisa Chandra , Mark Brown , Hao Luan , Ashish Rai Shrivastava
CPC classification number: G06F16/252 , G06F13/4022 , G06F15/7814 , G06F16/254 , G06F16/283
Abstract: A computation system-on-a-chip (CSoC) includes a first scalable distributed real-time Data Warehousing (sdrDW) engine and a network interface coupled to the first sdrDW engine, where the network interface is coupled to an interconnect, and where the CSoC is configured to transmit a task request over the interconnect to a first networked bulk storage controller (NBSC) requesting that a task be performed on a bulk storage medium.
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公开(公告)号：US20170293587A1
公开(公告)日：2017-10-12
申请号：US15096982
申请日：2016-04-12
Applicant: Futurewei Technologies, Inc.
Inventor： Peter Yan , Alex Elisa Chandra , YwhPyng Harn , Xiaotao Chen , Alan Gatherer , Fang Yu , Xingfeng Chen , Zhuolei Wang , Yang Zhou
CPC classification number: G06F13/4265 , G06F13/4022 , G06F13/4045 , Y02D10/14 , Y02D10/151
Abstract: A described embodiment of the present invention includes a network having a first, second an d third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.
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公开(公告)号：US20170168792A1
公开(公告)日：2017-06-15
申请号：US15378714
申请日：2016-12-14
Applicant: Futurewei Technologies, Inc.
Inventor： Debashis Bhattacharya , Alan Gatherer , Mark Brown , Lee Dobson McFearin , Alex Elisa Chandra , Ashish Rai Shrivastava
IPC: G06F9/45
CPC classification number: G06F8/51
Abstract: A method includes obtaining, by a first processor, a first software architecture description file and obtaining, by the first processor, a platform independent model file. The method also includes obtaining, by the first processor, a platform architecture definition file and performing, by the first processor, a first source-to-source compilation in accordance with the first software architecture description file, the platform independent model file, and the platform architecture definition file, to produce generated interface code. Additionally, the method includes generating, by the first processor, run time code, in accordance with the generated interface code and running, by a second processor in real time, the run time code.
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公开(公告)号：US20160103707A1
公开(公告)日：2016-04-14
申请号：US14877155
申请日：2015-10-07
Applicant: Futurewei Technologies, Inc.
Inventor： Debashis Bhattacharya , Alan Gatherer , Ashish Rai Shrivastava , Mark Brown , Zhenguo Gu , Qiang Wang , Alex Elisa Chandra
CPC classification number: G06F9/4881 , G06F9/44505
Abstract: A method includes receiving, by a system on a chip (SoC) from a logically centralized controller, configuration information and reading, from a semantics aware storage module of the SoC, a data block in accordance with the configuration information. The method also includes performing scheduling to produce a schedule in accordance with the configuration information and writing the data block to an input data queue in accordance with the schedule to produce a stored data block. Additionally, the method includes writing a tag to an input tag queue to produce a stored tag, where the tag corresponds to the data block.
Abstract translation: 一种方法包括：通过来自逻辑中央控制器的芯片上的系统（SoC）从SoC的语义感知存储模块接收配置信息和根据配置信息读取数据块。 该方法还包括执行调度以根据配置信息产生调度，并且根据调度将数据块写入输入数据队列以产生存储的数据块。 此外，该方法包括将标签写入输入标签队列以产生存储的标签，其中标签对应于数据块。
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