公开(公告)号：US20220164115A1

公开(公告)日：2022-05-26

申请号：US17543024

申请日：2021-12-06

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Lee Dobson McFearin ,  Alan Gatherer ,  Hao Luan

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/14 ,  G06F12/0888 ,  G06F12/084

Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

公开(公告)号：US11194478B2

公开(公告)日：2021-12-07

申请号：US16658899

申请日：2019-10-21

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Lee Dobson McFearin ,  Alan Gatherer ,  Hao Luan

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/14 ,  G06F12/0888 ,  G06F12/084 ,  G06F12/0815

Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

公开(公告)号：US10817528B2

公开(公告)日：2020-10-27

申请号：US15365755

申请日：2016-11-30

Applicant: Futurewei Technologies, Inc.

Inventor： Ashish Rai Shrivastava ,  Alex Elisa Chandra ,  Mark Brown ,  Debashis Bhattacharya ,  Alan Gatherer

IPC: G06F16/25 ,  G06F16/21 ,  G06F16/28

Abstract: A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.

公开(公告)号：US10691463B2

公开(公告)日：2020-06-23

申请号：US15220067

申请日：2016-07-26

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alan Gatherer ,  Ashish Rai Shrivastava

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.

公开(公告)号：US10289598B2

公开(公告)日：2019-05-14

申请号：US15096982

申请日：2016-04-12

Applicant: Futurewei Technologies, Inc.

Inventor： Peter Yan ,  Alex Elisa Chandra ,  YwhPyng Harn ,  Xiaotao Chen ,  Alan Gatherer ,  Fang Yu ,  Xingfeng Chen ,  Zhuolei Wang ,  Yang Zhou

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40

Abstract: A described embodiment of the present invention includes a network having a first, second and third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.

公开(公告)号：US20180300258A1

公开(公告)日：2018-10-18

申请号：US15486699

申请日：2017-04-13

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alex Elisa Chandra ,  Alan Gatherer

IPC: G06F12/126

Abstract: A method of operating a cache memory comprises receiving a first read or write command including at least a first address referring to first data and a first rank indicator associated with the first data, and in response to receiving the first read or write command, reading or writing the first data referenced by the first address, and storing the first rank indicator.

公开(公告)号：US20180285290A1

公开(公告)日：2018-10-04

申请号：US15942065

申请日：2018-03-30

Applicant: Futurewei Technologies, Inc.

Inventor： Hao Luan ,  Alan Gatherer ,  Xi Chen ,  Fang Yu ,  Yichuan Yu ,  Bin Yang ,  Wei Chen

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

公开(公告)号：US20170300414A1

公开(公告)日：2017-10-19

申请号：US15131779

申请日：2016-04-18

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alan Gatherer ,  Ashish Rai Shrivastava

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0877

Abstract: A cache and a method for operating a cache are disclosed. In an embodiment, the cache includes a cache controller, data cache and a delay write through cache (DWTC), wherein the data cache is separate and distinct from the DWTC, wherein cacheable write accesses are split into shareable cacheable write accesses and non-shareable cacheable write accesses, wherein the cacheable shareable write accesses are allocated only to the DWTC, and wherein the non-shareable cacheable write accesses are not allocated to the DWTC.

公开(公告)号：US20170293512A1

公开(公告)日：2017-10-12

申请号：US15096966

申请日：2016-04-12

Applicant: Futurewei Technologies, Inc.

Inventor： Peter Yan ,  Alan Gatherer ,  Alex Elisa Chandra ,  Lee Dobson Mcfearin ,  Mark Brown ,  Debashis Bhattacharya ,  Fang Yu ,  Xingfeng Chen ,  Yan Bei ,  Ke Ning ,  Chushun Huang ,  Tong Sun ,  Xiaotao Chen

IPC: G06F9/54 ,  G06F13/28

CPC classification number: G06F9/546 ,  G06F13/28

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

公开(公告)号：US20170206173A1

公开(公告)日：2017-07-20

申请号：US14997026

申请日：2016-01-15

Applicant: Futurewei Technologies, Inc.

Inventor： Lee McFearin ,  Sushma Wokhlu ,  Alan Gatherer

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/121 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/1044 ,  G06F2212/60

Abstract: The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.