公开(公告)号：US11954058B2

公开(公告)日：2024-04-09

申请号：US17747151

申请日：2022-05-18

Applicant: Futurewei Technologies, Inc.

Inventor： Wesley Shao

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4045 ,  G06F13/4221 ,  G06F2213/0026

Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

公开(公告)号：US10216676B2

公开(公告)日：2019-02-26

申请号：US16010235

申请日：2018-06-15

Applicant: Futurewei Technologies, inc.

Inventor： Wesley Shao

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

公开(公告)号：US20180300276A1

公开(公告)日：2018-10-18

申请号：US16010199

申请日：2018-06-15

Applicant: Futurewei Technologies, inc.

Inventor： Wesley Shao

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4045 ,  G06F13/4221 ,  G06F2213/0026

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

公开(公告)号：US20160306744A1

公开(公告)日：2016-10-20

申请号：US14688718

申请日：2015-04-16

Applicant: Futurewei Technologies, Inc.

Inventor： Mark Allan Kampe ,  Cameron Bahar ,  Jinshui Liu ,  Wesley Shao ,  Huawei Liu

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F3/0683 ,  G06F3/0619 ,  G06F3/065 ,  G06F11/00

Abstract: A method for operating a device adapted to store information with high reliability includes determining a storage address for a data payload portion of a write request in accordance with a configuration of a communications interface coupled to the device, where the data payload is to be stored in mirroring groups of cache storage partitions of a plurality of cache storage modules. The method also includes generating a payload read request in accordance with the storage address, and prompting the communications interface to initiate the storing of the data payload, in parallel, in the mirroring groups in accordance with the payload read request.

Abstract translation: 用于操作适于存储具有高可靠性的信息的设备的方法包括根据耦合到该设备的通信接口的配置来确定写请求的数据有效载荷部分的存储地址，其中数据有效载荷将被存储在 多个高速缓存存储模块的高速缓存存储分区的镜像组。 该方法还包括根据存储地址生成有效载荷读取请求，并且根据有效载荷读取请求，提示通信接口并行地启动对镜像组中的数据有效载荷的存储。

公开(公告)号：US20160098372A1

公开(公告)日：2016-04-07

申请号：US14873995

申请日：2015-10-02

Applicant: Futurewei Technologies, Inc.

Inventor： Thomas Boyle ,  Chang Yu ,  Wesley Shao ,  Ligang Chen

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4072 ,  G06F13/4282

Abstract: A method for accessing a device in a primary peripheral component interconnect express (PCIe) domain from a secondary PCIe domain includes determining which one or more virtual functions of the device in the primary PCIe domain are to be made available to the secondary PCIe domain. A virtual function driver is installed in the primary PCIe domain associated with the one or more virtual functions. Information corresponding to the one or more virtual functions is provided to the secondary PCIe domain. A virtual function driver associated with the one or more virtual functions is installed in the secondary PCIe domain from the information. The virtual function driver in the secondary PCIe domain has same properties as the virtual function driver in the primary PCIe domain. The device in the primary PCIe domain is accessed from the virtual function driver in the secondary PCIe domain.

Abstract translation: 用于从辅助PCIe域访问主外设组件互连快递（PCIe）域中的设备的方法包括确定主PCIe域中的设备的哪一个或多个虚拟功能将被提供给辅助PCIe域。 虚拟功能驱动程序安装在与一个或多个虚拟功能相关联的主PCIe域中。 与一个或多个虚拟功能相对应的信息被提供给辅助PCIe域。 与该一个或多个虚拟功能相关联的虚拟功能驱动程序从信息安装在辅助PCIe域中。 辅助PCIe域中的虚拟功能驱动程序与主PCIe域中的虚拟功能驱动程序具有相同的属性。 主PCIe域中的设备可从辅助PCIe域中的虚拟功能驱动程序访问。

公开(公告)号：US11429550B2

公开(公告)日：2022-08-30

申请号：US17153639

申请日：2021-01-20

Applicant: Futurewei Technologies, Inc.

Inventor： Wesley Shao

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

公开(公告)号：US10417160B2

公开(公告)日：2019-09-17

申请号：US16010199

申请日：2018-06-15

Applicant: Futurewei Technologies, Inc.

Inventor： Wesley Shao

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

公开(公告)号：US09870177B2

公开(公告)日：2018-01-16

申请号：US14688718

申请日：2015-04-16

Applicant: Futurewei Technologies, Inc.

Inventor： Mark Allan Kampe ,  Cameron Bahar ,  Jinshui Liu ,  Wesley Shao ,  Huawei Liu

IPC: G06F3/06 ,  G06F11/00

CPC classification number: G06F3/0683 ,  G06F3/0619 ,  G06F3/065 ,  G06F11/00

Abstract: A method for operating a device adapted to store information with high reliability includes determining a storage address for a data payload portion of a write request in accordance with a configuration of a communications interface coupled to the device, where the data payload is to be stored in mirroring groups of cache storage partitions of a plurality of cache storage modules. The method also includes generating a payload read request in accordance with the storage address, and prompting the communications interface to initiate the storing of the data payload, in parallel, in the mirroring groups in accordance with the payload read request.

公开(公告)号：US20150006780A1

公开(公告)日：2015-01-01

申请号：US13931640

申请日：2013-06-28

Applicant: FutureWei Technologies, Inc.

Inventor： Wesley Shao

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4045 ,  G06F13/4221 ,  G06F2213/0026

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract translation: 扩展外围组件互连快速（PCIe）设备的示例性实施例包括包含主机根复合体的主机PCIe结构。 主机PCIe架构具有第一组总线编号和主机CPU上的第一个内存映射输入/输出（MMIO）空间。 扩展的PCIe结构包括作为主机PCIe结构端点的一部分的根复合端点（RCEP）。 扩展的PCIe结构具有第二组总线编号和分别与第一组总线编号和第一MMIO空间分开的第二MMIO空间。

公开(公告)号：US20210216485A1

公开(公告)日：2021-07-15

申请号：US17153639

申请日：2021-01-20

Applicant: Futurewei Technologies, Inc.

Inventor： Wesley Shao

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.