公开(公告)号：US08370684B2

公开(公告)日：2013-02-05

申请号：US12944269

申请日：2010-11-11

申请人： G. Glenn Henry ,  Darius D. Gaskins ,  Jason Chen

发明人： G. Glenn Henry ,  Darius D. Gaskins ,  Jason Chen

IPC分类号： G06F11/26

CPC分类号： G06F11/3648

摘要： A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.

摘要翻译： 微处理器包括总线接口单元，该总线接口单元将微处理器连接到总线，总线包括一个信号，当被断言时，它指示所有总线代理人不要发起总线事务。 微代码使得总线接口单元响应于检测到事件而声明信号并复位微处理器，但不会重置总线接口单元的断言总线上的信号的部分。 复位后，微码使总线接口单元解除总线上的信号。 此外，微代码设置一个标志，并在复位本身之前将微处理器状态保存到存储器中，但不会将中断控制器复位。 复位后，微码从存储器重新加载微处理器的状态。 然而，如果微码确定标志被设置，它将放弃重新加载中断控制器的状态。

公开(公告)号：US20110202796A1

公开(公告)日：2011-08-18

申请号：US12944269

申请日：2010-11-11

申请人： G. Glenn Henry ,  Darius D. Gaskins ,  Jason Chen

发明人： G. Glenn Henry ,  Darius D. Gaskins ,  Jason Chen

IPC分类号： G06F11/00 ,  G06F13/28 ,  G06F13/24

CPC分类号： G06F11/3648

摘要： A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.

摘要翻译： 微处理器包括总线接口单元，该总线接口单元将微处理器连接到总线，总线包括一个信号，当被断言时，它指示所有总线代理人不要发起总线事务。 微代码使得总线接口单元响应于检测到事件而声明信号并复位微处理器，但不会重置总线接口单元的断言总线上的信号的部分。 复位后，微码使总线接口单元解除总线上的信号。 此外，微代码设置一个标志，并在复位本身之前将微处理器状态保存到存储器中，但不会将中断控制器复位。 复位后，微码从存储器重新加载微处理器的状态。 然而，如果微码确定标志被设置，它将放弃重新加载中断控制器的状态。

公开(公告)号：US08782451B2

公开(公告)日：2014-07-15

申请号：US13299059

申请日：2011-11-17

申请人： G. Glenn Henry ,  Darius D. Gaskins

发明人： G. Glenn Henry ,  Darius D. Gaskins

IPC分类号： G06F1/32 ,  G06F9/50

CPC分类号： G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

摘要： A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.

摘要翻译： 多核处理器包括分布在每个核心中的微码，使得每个核心能够参与去集中的核心间状态发现过程。 在相关的微代码实现方法中，多核处理器的状态由参与去集中式核心状态发现过程的至少两个核心发现。 通过在每个参与核心上执行的微代码和通过边带非系统总线通信线路在核心之间交换的信号的组合来执行核心间状态发现处理。 发现过程不受任何集中式非核心逻辑的介入。 适用的可发现状态包括目标和复合功率状态，是否启用多少个核心，启用各种资源的可用性和分配，以及核心的分层结构和协调系统。 核心状态发现过程可以根据涉及链接的核心间通信的各种分层协调系统来执行。

公开(公告)号：US08635476B2

公开(公告)日：2014-01-21

申请号：US13299122

申请日：2011-11-17

申请人： G. Glenn Henry ,  Darius D. Gaskins

发明人： G. Glenn Henry ,  Darius D. Gaskins

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/22

摘要： A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic.

摘要翻译： 多核处理器提供由两个或多个核共享的可配置资源，其中该资源的配置影响共享该资源的核能够运行的功率，速度或效率。 内部核心电源状态管理逻辑配置每个内核参与一个非集中式的核心间电源状态发现过程，以发现一个最不受干扰任何限制或功率节省状态的共享资源的复合目标电源状态 的每个核心共享资源的相应目标电源状态。 内部核心电源状态管理逻辑确定核心是否是授权配置资源的主核心，如果是，则在发现的组合电源状态下配置该资源。 集中式电源状态发现过程在边带核心之间，非系统总线线路上进行，无需集中式非核心逻辑。

公开(公告)号：US08615672B2

公开(公告)日：2013-12-24

申请号：US13157555

申请日：2011-06-10

申请人： G. Glenn Henry ,  Darius D. Gaskins ,  Stephan Gaskins

发明人： G. Glenn Henry ,  Darius D. Gaskins ,  Stephan Gaskins

IPC分类号： G06F1/00 ,  G06F11/30

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A microprocessor includes two or more processing cores each configured to determine, at each of succeeding instances in time, an amount of energy consumed by the microprocessor during a period preceding the instance in time. The period is predetermined. Each core also operates at a frequency above a predetermined frequency in response to determining the amount of energy consumed is less than a predetermined amount of energy. All of the cores may operate above the predetermined frequency simultaneously until one of the cores determines the microprocessor has consumed more than the predetermined amount of energy during the period preceding the instance in time. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined period without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate.

摘要翻译： 微处理器包括两个或更多个处理核心，每个处理核心被配置为在时间上的每个后续实例中确定微处理器在时间之前的时间段期间消耗的能量的量。 期限是预定的。 响应于确定消耗的能量量小于预定量的能量，每个核心还以高于预定频率的频率工作。 所有的核心可以同时工作在预定频率上方，直到核心之一确定微处理器在时间之前的时间段内消耗超过预定量的能量。 预定频率可以是：在所有核心可以在预定时间段内操作而不使微处理器消耗大于预定量的能量的频率，或者替代地，系统软件可以请求核心操作的最大频率。

公开(公告)号：US08276032B2

公开(公告)日：2012-09-25

申请号：US12719260

申请日：2010-03-08

申请人： G. Glenn Henry ,  Darius D. Gaskins ,  Stephan Gaskins

发明人： G. Glenn Henry ,  Darius D. Gaskins ,  Stephan Gaskins

IPC分类号： G01R31/28

CPC分类号： G06F11/10 ,  G06F11/2236

摘要： A microprocessor includes a first plurality of fuses, a predetermined number of which are selectively blown. Control values are provided from the first plurality of fuses to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, blown with the predetermined number of the first plurality of fuses that are blown. In response to being reset, the microprocessor is configured to: read the first plurality of fuses and count a number of them that are blown; read the predetermined number from the second plurality of fuses; compare the counted number with the predetermined number read from the second plurality of fuses; and prevent itself from fetching and executing user program instructions if the number counted from reading the first plurality of fuses does not equal the predetermined number read from the second plurality of fuses.

摘要翻译： 微处理器包括第一组多个保险丝，预定数量的保险丝被选择性地吹制。 控制值从第一组多个保险丝提供给微处理器的电路以控制微处理器的操作。 微处理器还包括第二组多个保险丝，其与预定数量的第一组熔断器熔断一起。 响应于复位，微处理器被配置为：读取第一组多个保险丝并对其中的数量进行计数; 从第二组保险丝读出预定数量; 将所计数的数量与从所述第二多个保险丝读取的预定数量进行比较; 并且如果从读取第一多个保险丝计数的数量不等于从第二多个保险丝读取的预定数量，则防止其取出并执行用户程序指令。

公开(公告)号：US20120047385A1

公开(公告)日：2012-02-23

申请号：US13157555

申请日：2011-06-10

申请人： G. Glenn Henry ,  Darius D. Gaskins ,  Stephan Gaskins

发明人： G. Glenn Henry ,  Darius D. Gaskins ,  Stephan Gaskins

IPC分类号： G06F1/28

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A microprocessor includes two or more processing cores each configured to determine, at each of succeeding instances in time, an amount of energy consumed by the microprocessor during a period preceding the instance in time. The period is predetermined. Each core also operates at a frequency above a predetermined frequency in response to determining the amount of energy consumed is less than a predetermined amount of energy. All of the cores may operate above the predetermined frequency simultaneously until one of the cores determines the microprocessor has consumed more than the predetermined amount of energy during the period preceding the instance in time. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined period without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate.

摘要翻译： 微处理器包括两个或更多个处理核心，每个处理核心被配置为在时间上的每个后续实例中确定微处理器在时间之前的时间段期间消耗的能量的量。 期限是预定的。 响应于确定消耗的能量量小于预定量的能量，每个核心还以高于预定频率的频率工作。 所有的核心可以同时工作在预定频率上方，直到核心之一确定微处理器在时间之前的时间段内消耗超过预定量的能量。 预定频率可以是：在所有核心可以在预定时间段内操作而不使微处理器消耗大于预定量的能量的频率，或者替代地，系统软件可以请求核心操作的最大频率。

公开(公告)号：US20120047377A1

公开(公告)日：2012-02-23

申请号：US13157498

申请日：2011-06-10

申请人： G. Glenn Henry ,  Darius D. Gaskins ,  Stephan Gaskins

发明人： G. Glenn Henry ,  Darius D. Gaskins ,  Stephan Gaskins

IPC分类号： G06F1/28

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A microprocessor includes an input that receives an indication of the amount of instantaneous power being supplied to the microprocessor by an external power source. The microprocessor includes a plurality of processing cores that each receive the indication from the input and responsively determine an amount of energy consumed by the microprocessor during a preceding period. The period is a predetermined length of time. Each processing core operates at a frequency above a predetermined frequency in response to determining that the amount of energy consumed by the microprocessor during the preceding period is less than a predetermined amount of energy. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the two or more processing cores to operate.

摘要翻译： 微处理器包括一个输入，该输入接收由外部电源提供给微处理器的瞬时功率量的指示。 微处理器包括多个处理核心，每个处理核心从输入端接收指示，并且响应地确定微处理器在前一时段期间消耗的能量的量。 该期间是预定的时间长度。 响应于确定微处理器在前一周期中消耗的能量的量小于预定量的能量，每个处理核心以高于预定频率的频率工作。 预定频率可以是：所有核心可以在预定时间长度上操作而不使微处理器消耗大于预定量的能量的频率，或者替代地，系统软件可以请求两个或多个处理核心的最大频率 操作。

公开(公告)号：US08631256B2

公开(公告)日：2014-01-14

申请号：US13299225

申请日：2011-11-17

申请人： G. Glenn Henry ,  Darius D. Gaskins

发明人： G. Glenn Henry ,  Darius D. Gaskins

IPC分类号： G06F1/26

CPC分类号： G06F1/06 ,  G06F1/3296 ,  Y02D10/172

摘要： Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.

摘要翻译： 微处理器具有分散逻辑和相关联的方法，用于将功率相关的操作状态（例如期望的电压和频率比）指示给诸如电压调节器模块（VRM）和锁相环（PLL）的共享微处理器功率资源。 每个核心被配置为产生一个值以指示所述核心的期望操作状态。 每个核心还被配置为从彼此分配可用资源的核心接收相应的值，并且计算与共享可应用资源的每个核心的最小需求兼容的复合值。 每个核心还被配置为基于是否将核心指定为主核以有条件地将核心的复合值驱动到适用的资源，以便控制或协调适用的资源。 复合值被提供给可应用的共享资源，而不使用多个核之外的任何活动逻辑。

公开(公告)号：US6081853A

公开(公告)日：2000-06-27

申请号：US34556

申请日：1998-03-03

申请人： Darius D. Gaskins ,  G. Glenn Henry

发明人： Darius D. Gaskins ,  G. Glenn Henry

IPC分类号： G06F12/08 ,  G06F12/06

CPC分类号： G06F12/0859 ,  G06F12/0879 ,  G06F12/0851

摘要： A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache line has L/W banks, the lowermost bank being in an odd position and the uppermost bank being in an even position. In a request for a particular data entity, a series of addresses are issued on the address bus to fill the associated cache line. The first address is always for a particular cache bank to which the particular data entity is mapped. The remaining addresses are sequenced ascending linearly, modulo L. If the particular data entity is mapped to an even cache bank, but not to the uppermost cache bank, then L/W remaining addresses are issued, beginning with the base address of the cache bank immediately following the cache bank to which the particular data entity is mapped.

摘要翻译： 提供了一种用于处理系统中的数据的突发传送的方法。 处理系统具有W字节（W even）的数据总线宽度和L字节（L even）的高速缓存行长度。 高速缓存线具有L / W组，最下面的组处于奇数位置，最上面的组位于偶数位置。 在对特定数据实体的请求中，在地址总线上发出一系列地址以填充关联的高速缓存行。 第一个地址总是针对特定数据实体映射到的特定缓存库。 剩下的地址按线性递增排序，如果特定的数据实体被映射到偶数缓存组而不是最上层的高速缓存组，那么从缓存组的基地址开始输出L / W剩余的地址 紧跟在特定数据实体映射到的缓存库之后。