公开(公告)号：US4915779A

公开(公告)日：1990-04-10

申请号：US235134

申请日：1988-08-23

申请人： G. Scot Srodes ,  Willis R. Goodner ,  John L. Freeman, Jr. ,  Andrew G. Nagy

发明人： G. Scot Srodes ,  Willis R. Goodner ,  John L. Freeman, Jr. ,  Andrew G. Nagy

IPC分类号： C23F4/00 ,  H01L21/3213

CPC分类号： H01L21/32136 ,  C23F4/00 ,  Y10S438/95

摘要： A residue-free plasma etch of high temperature aluminum copper metallization is provided by the use of a single plasma etcher. The metallization layer is covered by a protective oxide layer. This structure is then placed in the single etcher and a vacuum is established. The protective oxide layer is then etched and without breaking the vacuum or removing the structure from the etcher the metal layer is also etched. This results in the etched surface being residue-free.

摘要翻译： 通过使用单个等离子体蚀刻器提供高温铝铜金属化的无残留等离子体蚀刻。 金属化层被保护性氧化物层覆盖。 然后将该结构放置在单个蚀刻器中并建立真空。 然后蚀刻保护性氧化物层并且不破坏真空或从蚀刻器去除结构，金属层也被蚀刻。 这导致蚀刻表面无残留。

公开(公告)号：US4621045A

公开(公告)日：1986-11-04

申请号：US740790

申请日：1985-06-03

申请人： Willis R. Goodner

发明人： Willis R. Goodner

IPC分类号： H01L21/768 ,  B44C1/22

CPC分类号： H01L21/76885 ,  H01L21/76819

摘要： A method is described for providing a conductive pillar in a via between multiple layers of conductors on planar electronic structures such as integrated circuits while at the same time exposing other large area contact regions such as a bonding pad. A first conductor layer is formed on the device substrate, etched to delineate the bonding pad and the first level interconnects, and covered with a differentially etchable intermediate conductive material which is delineated to form the conductive pillar. A dielectric planarizing layer is applied so as to have a smooth surface contour and a lower thickness above the conductive pillar than over the first level interconnects or the bonding pad. The planarizing dielectric is desirably a negative acting radiation sensitive material such as a polyimide. A mask is used to render the portions of this dielectric planarizing layer above the bonding pad soluble so that it may be dissolved away while leaving the remainder undisturbed. The resulting structure is then blanket etched to remove the smaller thickness of dielectric layer above the top of the pillar. The dielectric surface and pillar surface smoothly join. Another conductive layer is then applied over the surface of the dielectric planarizing layer and in contact with the top of the pillar and patterned in the conventional manner to form the second level interconnects. The resulting structure has a relatively smooth surface topology and little or no step at the pillars.

摘要翻译： 描述了一种用于在平面电子结构（例如集成电路）上的多层导体之间的通孔中提供导电柱的方法，同时暴露诸如焊盘的其它大面积接触区域。 第一导体层形成在器件衬底上，被蚀刻以描绘接合焊盘和第一级互连，并被描绘成形成导电柱的可差分蚀刻的中间导电材料覆盖。 施加电介质平坦化层以在导电柱之上具有比在第一级互连或接合焊盘上方更平滑的表面轮廓和更低的厚度。 平坦化电介质优选为负型辐射敏感材料，例如聚酰亚胺。 掩模用于使该介电平面化层的部分在焊盘上方可溶，使得其可以溶解掉，同时使其余部分不受干扰。 然后将所得到的结构进行全面蚀刻以去除柱顶部上方的较小厚度的电介质层。 电介质表面和柱面平滑连接。 然后将另一导电层施加在电介质平坦化层的表面上并与柱的顶部接触并以常规方式图案化以形成第二级互连。 所得到的结构具有相对平滑的表面拓扑，并且在柱上几乎没有或没有台阶。

公开(公告)号：US4222839A

公开(公告)日：1980-09-16

申请号：US944427

申请日：1978-09-21

申请人： Willis R. Goodner ,  Joseph P. Y. Kao

发明人： Willis R. Goodner ,  Joseph P. Y. Kao

IPC分类号： C30B33/00 ,  C23F1/00 ,  B01K1/00

CPC分类号： C30B33/00

摘要： A holder and method for controlling and uniformly maintaining the temperature of work pieces when the work pieces are acted upon by a plasma in a plasma reactor apparatus. Support means which hold the work pieces so as to expose them to the reactive plasma also position metallic plate members which are capable of being heated to an elevated temperature by the plasma when in electrical contact with an electrode of the plasma reactor apparatus. The metallic plate members are all electrically shorted together, but are insulated from the support means. A temperature sensitive switch connects the metallic plate members to an electrode of the plasma apparatus. Work pieces to be acted upon by the plasma are placed in proximity to the metal plate members. In the presence of a plasma and when shorted to the apparatus electrode, the metallic plate members are rapidly heated and heat is conducted to the work pieces to heat them uniformly. The temperature of the work pieces is controlled by selectively opening and closing the temperature sensitive switch and thereby selectively shorting the metal members to the apparatus electrode. Little heating occurs when the switch is open and the members are isolated from the electrode.

摘要翻译： 一种用于在等离子体反应器装置中通过等离子体作用工件时控制和均匀地保持工件的温度的保持器和方法。 保持工件以便将它们暴露于反应性等离子体的支撑装置还定位当与等离子体反应器装置的电极电接触时能够被等离子体加热到升高的温度的金属板构件。 金属板构件全部电短路在一起，但与支撑装置绝缘。 温度敏感开关将金属板构件连接到等离子体装置的电极。 待等离子体作用的工件被放置在金属板构件附近。 在等离子体的存在下，当与设备电极短路时，金属板构件被快速加热，并且热量被传导到工件以均匀地加热它们。 通过选择性地打开和关闭温度敏感开关来控制工件的温度，从而将金属构件选择性地短路到设备电极。 当开关打开并且构件与电极隔离时，几乎不发生加热。

公开(公告)号：US4523372A

公开(公告)日：1985-06-18

申请号：US607868

申请日：1984-05-07

申请人： Raymond J. Balda ,  Yefim Bukhman ,  Willis R. Goodner

发明人： Raymond J. Balda ,  Yefim Bukhman ,  Willis R. Goodner

IPC分类号： H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L21/312

CPC分类号： H01L21/76802 ,  H01L21/31138 ,  Y10S148/131 ,  Y10S438/945 ,  Y10S438/963

摘要： A process is disclosed for fabricating semiconductor devices, and especially for fabricating semiconductor devices having multiple levels of metallization separated by polyimide or other organic materials. The process avoids the sputter etching and redeposition of the lower metal layer during reactive ion etching of openings through the organic layer. Sequential layers overlying the first layer of metallization include a layer of oxide, a layer of organic material, and a second layer of oxide. The second layer of oxide functions as a hard mask for patterning the organic material. The first layer of oxide acts as an etch stop and protective layer to prevent attack of the underlying metal during reactive ion etching of the organic layer. The first layer of oxide is of limited areal extent to avoid subsequent problems with the organic layer. The oxide located at the bottom of the opening through the organic material as well as the second layer of oxide and any oxide which is sputtered and redeposited on the walls of the opening through the organic material are easily removed in a single etch step without adversely affecting the underlying metallization. After removing the oxide, a second layer of metallization is applied and patterned as required.

摘要翻译： 公开了用于制造半导体器件的方法，特别是用于制造具有由聚酰亚胺或其它有机材料分离的多层金属化的半导体器件。 该过程避免了在通过有机层的开口的反应离子蚀刻期间溅射蚀刻和再沉积下部金属层。 覆盖第一层金属化层的顺序层包括一层氧化物，一层有机材料和第二层氧化物层。 第二层氧化物用作图案化有机材料的硬掩模。 第一层氧化物用作蚀刻停止层和保护层，以防止在有机层的反应离子蚀刻期间底层金属的侵蚀。 第一层氧化物的面积有限，以避免有机层的后续问题。 通过有机材料位于开口底部的氧化物以及第二层氧化物和通过有机材料溅射并重新沉积在开口壁上的任何氧化物容易在单个蚀刻步骤中去除而不会不利地影响 底层金属化。 在去除氧化物之后，根据需要施加第二层金属化并图案化。