公开(公告)号：US4791073A

公开(公告)日：1988-12-13

申请号：US122094

申请日：1987-11-17

Applicant: Andrew G. Nagy ,  Robert J. Mattox

Inventor： Andrew G. Nagy ,  Robert J. Mattox

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/471 ,  H01L21/475

CPC classification number: H01L21/02063 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76224

Abstract: A method is described for forming dielectric filled isolation trenches in semiconductor substrates in which a differentially etchable etch-stop layer is provided above the surface of the substrate during the trench filling process so that the height of the trench filling relative to the surface of the substrate may be adjusted for optimum overall results during subsequent fabrication steps and so that the substrate surface may be protected from contact with the etching reagents used during planarization of the trench filling material. This avoids damage to the substrate surface and permits improved surface planarity.

公开(公告)号：US4915779A

公开(公告)日：1990-04-10

申请号：US235134

申请日：1988-08-23

Applicant: G. Scot Srodes ,  Willis R. Goodner ,  John L. Freeman, Jr. ,  Andrew G. Nagy

Inventor： G. Scot Srodes ,  Willis R. Goodner ,  John L. Freeman, Jr. ,  Andrew G. Nagy

IPC: C23F4/00 ,  H01L21/3213

CPC classification number: H01L21/32136 ,  C23F4/00 ,  Y10S438/95

Abstract: A residue-free plasma etch of high temperature aluminum copper metallization is provided by the use of a single plasma etcher. The metallization layer is covered by a protective oxide layer. This structure is then placed in the single etcher and a vacuum is established. The protective oxide layer is then etched and without breaking the vacuum or removing the structure from the etcher the metal layer is also etched. This results in the etched surface being residue-free.

Abstract translation: 通过使用单个等离子体蚀刻器提供高温铝铜金属化的无残留等离子体蚀刻。 金属化层被保护性氧化物层覆盖。 然后将该结构放置在单个蚀刻器中并建立真空。 然后蚀刻保护性氧化物层并且不破坏真空或从蚀刻器去除结构，金属层也被蚀刻。 这导致蚀刻表面无残留。

公开(公告)号：US07579228B2

公开(公告)日：2009-08-25

申请号：US11825953

申请日：2007-07-10

Applicant: Paul A. Grudowski ,  Kurt H. Junker ,  Thomas J. Kropewnicki ,  Andrew G. Nagy

Inventor： Paul A. Grudowski ,  Kurt H. Junker ,  Thomas J. Kropewnicki ,  Andrew G. Nagy

IPC: H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3146 ,  H01L21/823864 ,  H01L29/6653 ,  Y10S438/943

Abstract: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

Abstract translation: 提供一种制造半导体器件的方法，包括（a）提供包括第一栅电极（210）的半导体结构; （b）形成与所述第一电极相邻的第一组有机间隔物（213）; （c）在所述结构上沉积第一光掩模（215）; 和（d）同时去除第一组有机间隔物和第一光掩模。

公开(公告)号：US20090017587A1

公开(公告)日：2009-01-15

申请号：US11825953

申请日：2007-07-10

Applicant: Paul A. Grudowski ,  Kurt H. Junker ,  Thomas J. Kropewnicki ,  Andrew G. Nagy

Inventor： Paul A. Grudowski ,  Kurt H. Junker ,  Thomas J. Kropewnicki ,  Andrew G. Nagy

IPC: H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3146 ,  H01L21/823864 ,  H01L29/6653 ,  Y10S438/943

Abstract: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

公开(公告)号：US06686633B1

公开(公告)日：2004-02-03

申请号：US09653338

申请日：2000-08-31

Applicant: Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

Inventor： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC: H01L2976

CPC classification number: H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract translation: 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

公开(公告)号：US06184073B2

公开(公告)日：2001-02-06

申请号：US08997714

申请日：1997-12-23

Applicant: Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

Inventor： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC: H01L218234

CPC classification number: H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract translation: 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

公开(公告)号：US07521314B2

公开(公告)日：2009-04-21

申请号：US11738192

申请日：2007-04-20

Applicant: Dharmesh Jawarani ,  Konstantin V. Loiko ,  Andrew G. Nagy

Inventor： Dharmesh Jawarani ,  Konstantin V. Loiko ,  Andrew G. Nagy

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/4763

CPC classification number: H01L29/7843 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

Abstract: A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.

Abstract translation: 一种用于形成半导体器件的方法包括在包括控制电极的半导体材料上形成衬垫。 该方法还包括形成与控制电极相邻的第一间隔物，其中第一间隔物具有第一宽度。 该方法还包括植入电流电极掺杂剂。 该方法还包括移除第一间隔物。 该方法还包括形成邻近控制电极的第二间隔物，其中第二间隔物具有第二宽度，并且其中第二宽度小于第一宽度。 该方法还包括使用第二间隔件作为保护罩以选择性地移除衬垫。 该方法还包括形成覆盖控制电极和电流电极区域的应力源层。

公开(公告)号：US20080261385A1

公开(公告)日：2008-10-23

申请号：US11738192

申请日：2007-04-20

Applicant: Dharmesh Jawarani ,  Konstantin V. Loiko ,  Andrew G. Nagy

Inventor： Dharmesh Jawarani ,  Konstantin V. Loiko ,  Andrew G. Nagy

IPC: H01L21/311 ,  H01L21/266

CPC classification number: H01L29/7843 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

Abstract: A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.

Abstract translation: 一种用于形成半导体器件的方法包括在包括控制电极的半导体材料上形成衬垫。 该方法还包括形成与控制电极相邻的第一间隔物，其中第一间隔物具有第一宽度。 该方法还包括植入电流电极掺杂剂。 该方法还包括移除第一间隔物。 该方法还包括形成邻近控制电极的第二间隔物，其中第二间隔物具有第二宽度，并且其中第二宽度小于第一宽度。 该方法还包括使用第二间隔件作为保护罩以选择性地移除衬垫。 该方法还包括形成覆盖控制电极和电流电极区域的应力源层。

公开(公告)号：US4717446A

公开(公告)日：1988-01-05

申请号：US909043

申请日：1986-09-18

Applicant: Andrew G. Nagy ,  Donald K. Stemple ,  Clarence J. Tracy

Inventor： Andrew G. Nagy ,  Donald K. Stemple ,  Clarence J. Tracy

IPC: G01B11/06 ,  H01L21/66 ,  H01L21/306

CPC classification number: B24B37/013 ,  G01B11/0683 ,  H01L22/26

Abstract: A method of detecting the endpoint of expitaxially grown silicon using a monitor wafer is described. A monitor wafer having a substrate, an oxide layer, and a polysilicon layer is process in an epi chamber along with working wafers. The monitor wafer is used to determine the endpoint of the working wafers epi layer when the epi layer is etched.

Abstract translation: 描述了使用监视器晶片检测外延生长的硅的端点的方法。 具有衬底，氧化物层和多晶硅层的监测晶片与工作晶片一起在外延室中进行。 当外延层被蚀刻时，监测晶片用于确定工作晶片外延层的端点。