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    Process for fabricating semiconductor device
    1.
    发明授权
    Process for fabricating semiconductor device 失效
    半导体器件制造工艺

    公开(公告)号：US4523372A

    公开(公告)日：1985-06-18

    申请号：US607868

    申请日：1984-05-07

    申请人： Raymond J. Balda ,  Yefim Bukhman ,  Willis R. Goodner

    发明人： Raymond J. Balda ,  Yefim Bukhman ,  Willis R. Goodner

    IPC分类号： H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L21/312

    CPC分类号： H01L21/76802 ,  H01L21/31138 ,  Y10S148/131 ,  Y10S438/945 ,  Y10S438/963

    摘要： A process is disclosed for fabricating semiconductor devices, and especially for fabricating semiconductor devices having multiple levels of metallization separated by polyimide or other organic materials. The process avoids the sputter etching and redeposition of the lower metal layer during reactive ion etching of openings through the organic layer. Sequential layers overlying the first layer of metallization include a layer of oxide, a layer of organic material, and a second layer of oxide. The second layer of oxide functions as a hard mask for patterning the organic material. The first layer of oxide acts as an etch stop and protective layer to prevent attack of the underlying metal during reactive ion etching of the organic layer. The first layer of oxide is of limited areal extent to avoid subsequent problems with the organic layer. The oxide located at the bottom of the opening through the organic material as well as the second layer of oxide and any oxide which is sputtered and redeposited on the walls of the opening through the organic material are easily removed in a single etch step without adversely affecting the underlying metallization. After removing the oxide, a second layer of metallization is applied and patterned as required.

    摘要翻译： 公开了用于制造半导体器件的方法，特别是用于制造具有由聚酰亚胺或其它有机材料分离的多层金属化的半导体器件。 该过程避免了在通过有机层的开口的反应离子蚀刻期间溅射蚀刻和再沉积下部金属层。 覆盖第一层金属化层的顺序层包括一层氧化物，一层有机材料和第二层氧化物层。 第二层氧化物用作图案化有机材料的硬掩模。 第一层氧化物用作蚀刻停止层和保护层，以防止在有机层的反应离子蚀刻期间底层金属的侵蚀。 第一层氧化物的面积有限，以避免有机层的后续问题。 通过有机材料位于开口底部的氧化物以及第二层氧化物和通过有机材料溅射并重新沉积在开口壁上的任何氧化物容易在单个蚀刻步骤中去除而不会不利地影响 底层金属化。 在去除氧化物之后，根据需要施加第二层金属化并图案化。

    Method of manufacturing a semiconductor component
    2.
    发明授权
    Method of manufacturing a semiconductor component 有权
    制造半导体部件的方法

    公开(公告)号：US06489211B1

    公开(公告)日：2002-12-03

    申请号：US09516349

    申请日：2000-03-01

    申请人： John L. Freeman, Jr. ,  Raymond J. Balda ,  Robert A. Pryor ,  James D. Paulsen ,  Robert J. Johnsen

    发明人： John L. Freeman, Jr. ,  Raymond J. Balda ,  Robert A. Pryor ,  James D. Paulsen ,  Robert J. Johnsen

    IPC分类号： H01L218238

    CPC分类号： H01L29/66287 ,  H01L29/0649 ,  H01L29/66242

    摘要： A method of manufacturing a semiconductor component includes providing a composite substrate (300) with a dielectric portion and a semiconductor portion and growing an epitaxial layer (400) over the composite substrate. The epitaxial layer has a polycrystalline portion (402) over the dielectric portion of the composite substrate and also has a monocrystalline portion (401) over the semiconductor portion of the composite substrate. A first dopant is diffused into the monocrystalline portion of the epitaxial layer to form an emitter region in the monocrystalline portion of the epitaxial layer while a second dopant is simultaneously diffused into the monocrystalline portion of the epitaxial layer to form an enhanced portion of the base region.

    摘要翻译： 制造半导体部件的方法包括提供具有电介质部分和半导体部分的复合衬底（300），并在复合衬底上生长外延层（400）。 外延层在复合衬底的电介质部分上具有多晶部分（402），并且在复合衬底的半导体部分上还具有单晶部分（401）。 第一掺杂剂扩散到外延层的单晶部分中以在外延层的单晶部分中形成发射极区域，而第二掺杂剂同时扩散到外延层的单晶部分中，以形成基极区域的增强部分 。

    Integrated circuit structures having polycrystalline electrode contacts
    4.
    发明授权
    Integrated circuit structures having polycrystalline electrode contacts 失效
    具有多晶电极触点的集成电路结构

    公开(公告)号：US5067002A

    公开(公告)日：1991-11-19

    申请号：US304984

    申请日：1989-01-31

    申请人： Peter J. Zdebel ,  Raymond J. Balda ,  Bor-Yuan Hwang ,  Allen J. Wagner

    发明人： Peter J. Zdebel ,  Raymond J. Balda ,  Bor-Yuan Hwang ,  Allen J. Wagner

    IPC分类号： H01L21/033 ,  H01L21/225 ,  H01L21/285

    CPC分类号： H01L21/033 ,  H01L21/2257 ,  H01L21/28525

    摘要： A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

    摘要翻译： 公开了一种用于制造改进的集成电路器件的工艺。 根据本发明的一个实施例，通过在不依赖于限制性光刻公差的情况下产生小的器件区域的工艺来制造集成器件。 该方法使用四个多晶硅层来制造和接触器件区域，以实现相对平面的结构，并且将器件区域的尺寸减小到低于正常光刻公差的尺寸。 该过程使用主掩模来定义设备的基本占位面积，并与每个光刻步骤中易于对准的封锁掩模相结合。 还描述了可以同时制造的诸如互补横向和垂直双极晶体管，JFET，SIT，MOSFET，电阻器，二极管，电容器和其它器件的许多类型器件的手段和方法。