公开(公告)号：US20190157157A1

公开(公告)日：2019-05-23

申请号：US15821684

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahab Siddiqui ,  Beth Baumert ,  Abu Naser M. Zainuddin ,  Luigi Pantisano

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  C23C16/50 ,  C23C16/455

Abstract: At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.

公开(公告)号：US10438853B2

公开(公告)日：2019-10-08

申请号：US15821684

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahab Siddiqui ,  Beth Baumert ,  Abu Naser M. Zainuddin ,  Luigi Pantisano

IPC: H01L21/8234 ,  C23C16/455 ,  H01L21/02 ,  H01L21/28 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  C23C16/50

Abstract: At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.

公开(公告)号：US10361289B1

公开(公告)日：2019-07-23

申请号：US15933032

申请日：2018-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Shahab Siddiqui ,  Haiting Wang ,  Ting-Hsiang Hung ,  Yiheng Xu ,  Beth Baumert ,  Jinping Liu ,  Scott Beasor ,  Yue Zhong ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.

公开(公告)号：US10106892B1

公开(公告)日：2018-10-23

申请号：US15692816

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shahab Siddiqui ,  Abu Naser Zainuddin ,  Beth Baumert ,  Suresh Uppal

IPC: H01L21/02 ,  H01L21/306 ,  C23C16/455 ,  C01B33/149 ,  C01B21/06 ,  C01F7/02 ,  C01F17/00

Abstract: Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOx layer over the second silicon oxy-nitride layer and ILs.