公开(公告)号：US20180151238A1

公开(公告)日：2018-05-31

申请号：US15881356

申请日：2018-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  H01L27/112 ,  G11C17/18

CPC classification number: G11C17/12 ,  G11C17/18 ,  H01L27/11233

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

公开(公告)号：US09500703B2

公开(公告)日：2016-11-22

申请号：US14462643

申请日：2014-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anil Kumar ,  Suresh Uppal ,  Manjunatha Prabhu ,  William McMahon

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2601 ,  G01R31/2644 ,  H01L22/34

Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Abstract translation: 这里提出了包括多个测试装置的半导体结构，所述多个测试装置包括第一测试装置和第二测试装置。 半导体结构还可以包括波形发生电路，波形发生电路被配置为将第一应力信号波形具有第一占空比施加到第一测试装置，第二应力信号波形具有第二占空比到第二测试 设备。 半导体结构可以包括与第一测试装置和第二测试装置中的每一个相关联的选择电路，用于在应力循环和感测周期之间切换。

公开(公告)号：US20160061880A1

公开(公告)日：2016-03-03

申请号：US14473937

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suresh Uppal

IPC: G01R31/12 ,  G01R31/26 ,  G01R31/28

CPC classification number: G01R31/12 ,  G01R31/1227 ,  G01R31/3004 ,  G11C11/22 ,  G11C11/401 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/5002

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) on a plurality of devices. A first device and a second device are provided for testing. A test signal is provided for performing a time-dependent dielectric breakdown (TDDB) test on the first and second devices. A selection signal for selecting said first and second devices for performing said TDDB test. The first and second devices are arranged in series with a first resistor such that based upon said selecting, the test signal is applied substantially simultaneously to the first and second devices through the first resistor. A determination is made as to whether a breakdown and/or a failure of at least one of the first and second devices has occurred based upon a change in voltage across the first resistor.

Abstract translation: 本文公开的至少一种方法和系统涉及在多个设备上执行时间依赖介质击穿（TDDB）。 提供第一装置和第二装置用于测试。 提供测试信号用于在第一和第二器件上进行时间依赖介质击穿（TDDB）测试。 用于选择用于执行所述TDDB测试的所述第一和第二设备的选择信号。 第一和第二装置与第一电阻器串联布置，使得基于所述选择，测试信号基本上同时施加到第一和第二器件通过第一电阻器。 基于第一电阻器两端的电压变化，确定是否发生了第一和第二器件中的至少一个的故障和/或故障。

公开(公告)号：US20160005828A1

公开(公告)日：2016-01-07

申请号：US14321679

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  G01R31/26 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/66 ,  H01L21/762

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

Abstract translation: 本文公开的至少一种方法，装置和系统包括形成包括晶体管的器件，晶体管包括与有源栅极并联的至少一个非活性栅极。 形成基板上的源极区域。 在邻近源极区域的衬底上形成有源栅极区域。 在邻近有源栅极区的衬底上形成漏极区。 第一非活性栅极区域平行于有源栅极区域形成在衬底上。 源极区域，漏极区域，有源栅极区域和第一非活性栅极区域包括晶体管。 第一非活性栅极区域能够耗散电荷的至少一部分。

公开(公告)号：US10181713B2

公开(公告)日：2019-01-15

申请号：US14517605

申请日：2014-10-17

Applicant: GlobalFoundries, Inc.

Inventor： Arnaud Bousquet ,  Geetha Sai Aluri ,  Suresh Uppal

IPC: H02H3/08 ,  H01L21/66 ,  H01L21/8234 ,  H01L23/525 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02

Abstract: At least one method, apparatus and system disclosed herein involves providing an integrated circuit device comprising a protection circuit. And integrated circuit device is formed. A protection component is formed in parallel to the integrated circuit device. The protection component is configured for protecting the integrated circuit device from a portion of a charge. A circuit break device in series to the protection component, wherein the protection component and the circuit break device are in parallel to the integrated circuit device. The circuit break device is configured to break an electrical path of the protection component for electrically terminating the protection component based upon a current signal.

公开(公告)号：US09916903B2

公开(公告)日：2018-03-13

申请号：US14514289

申请日：2014-10-14

Applicant: GlobalFoundries Inc.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  H01L27/112 ,  G11C17/18

CPC classification number: G11C17/12 ,  G11C17/18 ,  H01L27/11233

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

公开(公告)号：US09324822B2

公开(公告)日：2016-04-26

申请号：US14321679

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/423 ,  H01L21/66 ,  H01L29/08 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  G01R31/26

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

Abstract translation: 本文公开的至少一种方法，装置和系统包括形成包括晶体管的器件，晶体管包括与有源栅极并联的至少一个非活性栅极。 形成基板上的源极区域。 在邻近源极区域的衬底上形成有源栅极区域。 在邻近有源栅极区的衬底上形成漏极区。 第一非活性栅极区域平行于有源栅极区域形成在衬底上。 源极区域，漏极区域，有源栅极区域和第一非活性栅极区域包括晶体管。 第一非活性栅极区域能够耗散电荷的至少一部分。

公开(公告)号：US20160111867A1

公开(公告)日：2016-04-21

申请号：US14517605

申请日：2014-10-17

Applicant: GlobalFoundries, Inc.

Inventor： Arnaud Bousquet ,  Geetha Sai Aluri ,  Suresh Uppal

IPC: H02H3/08 ,  H01L23/525 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/66 ,  H01L27/02

CPC classification number: H02H3/08 ,  H01L22/14 ,  H01L23/5256 ,  H01L27/0255 ,  H01L29/6609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one method, apparatus and system disclosed herein involves providing an integrated circuit device comprising a protection circuit. And integrated circuit device is formed. A protection component is formed in parallel to the integrated circuit device. The protection component is configured for protecting the integrated circuit device from a portion of a charge. A circuit break device in series to the protection component, wherein the protection component and the circuit break device are in parallel to the integrated circuit device. The circuit break device is configured to break an electrical path of the protection component for electrically terminating the protection component based upon a current signal.

Abstract translation: 本文公开的至少一种方法，装置和系统涉及提供包括保护电路的集成电路装置。 并形成集成电路器件。 保护部件与集成电路器件并联形成。 保护部件被配置为保护集成电路器件免受电荷的一部分的影响。 一种与保护部件串联的断路装置，其中保护部件和断路装置与集成电路装置并联。 断路装置被配置为基于电流信号中断保护部件的电气路径以电气端接保护部件。

公开(公告)号：US20150346271A1

公开(公告)日：2015-12-03

申请号：US14288278

申请日：2014-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh Uppal ,  Andreas Kerber ,  William McMahon

IPC: G01R31/26 ,  G01R31/12

CPC classification number: G01R31/129 ,  G01R31/2607 ,  G01R31/2623 ,  G01R31/2642 ,  G01R31/2874

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

Abstract translation: 本文公开的至少一种方法和系统涉及在器件上执行时间依赖介电击穿（TDDB）测试和偏置温度不稳定性（BTI）测试。 提供具有至少一个晶体管和至少一个电介质层的器件。 提供测试信号用于在设备上执行TDDB测试和BTI测试。 基于测试信号，在设备上基本上同时执行TDDB测试和BTI测试。 获取，存储和/或发送与介电层的击穿和基于TDDB测试和BTI测试的晶体管的至少一个特性相关的数据。

公开(公告)号：US10012687B2

公开(公告)日：2018-07-03

申请号：US14473937

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suresh Uppal

IPC: G01R31/12 ,  G01R31/26 ,  G01R31/28 ,  G11C29/50 ,  G01R31/30 ,  G11C11/22 ,  G11C11/401

CPC classification number: G01R31/12 ,  G01R31/1227 ,  G01R31/3004 ,  G11C11/22 ,  G11C11/401 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/5002

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) on a plurality of devices. A first device and a second device are provided for testing. A test signal is provided for performing a time-dependent dielectric breakdown (TDDB) test on the first and second devices. A selection signal for selecting said first and second devices for performing said TDDB test. The first and second devices are arranged in series with a first resistor such that based upon said selecting, the test signal is applied substantially simultaneously to the first and second devices through the first resistor. A determination is made as to whether a breakdown and/or a failure of at least one of the first and second devices has occurred based upon a change in voltage across the first resistor.