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公开(公告)号：US10585346B2
公开(公告)日：2020-03-10
申请号：US15819213
申请日：2017-11-21
Inventor： Chieh-Yu Lin , Dongbing Shao , Kehan Tian , Zheng Xu
Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
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公开(公告)号：US10394116B2
公开(公告)日：2019-08-27
申请号：US15696505
申请日：2017-09-06
Inventor： Chieh-Yu Lin , Dongbing Shao , Kehan Tian , Zheng Xu
Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
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3.发明申请公开(公告)号：US20170228491A1
公开(公告)日：2017-08-10
申请号：US15040453
申请日：2016-02-10
Applicant: GLOBALFOUNDRIES INC.
Inventor： James A. Culp , Chieh-Yu Lin , Dongbing Shao
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5009 , G06F17/5068 , G06F2217/12 , G06F2217/16
Abstract: Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.
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4.发明授权公开(公告)号：US09898573B2
公开(公告)日：2018-02-20
申请号：US15040453
申请日：2016-02-10
Applicant: GLOBALFOUNDRIES INC.
Inventor： James A. Culp , Chieh-Yu Lin , Dongbing Shao
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5009 , G06F17/5068 , G06F2217/12 , G06F2217/16
Abstract: Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.
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