公开(公告)号：US09638581B2

公开(公告)日：2017-05-02

申请号：US14302934

申请日：2014-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas G. Clore ,  Kendra A. Lyons ,  Andrew H. Norfleet ,  Jared P. Yanofsky

IPC: G01R31/26 ,  H01L21/66 ,  G01J5/08 ,  G01J5/02 ,  G01J5/00 ,  G01J5/28

CPC classification number: G01J5/0878 ,  G01J5/0007 ,  G01J5/025 ,  G01J2005/0085 ,  G01J2005/283 ,  H01L22/12 ,  H01L22/20 ,  H01L22/34

Abstract: According to embodiments of the present invention, a semiconductor substrate is formed on at least a portion of a surface of a semiconductor substrate. The emitting layer is excited for a first predetermined time period. A first luminescent intensity value of the emitting layer is determined. In response to exposing the semiconductor substrate and the emitting layer to a condition for a second predetermined time period, a second luminescent intensity value of the emitting layer is determined. A thermal profile of at least the portion of the surface of the semiconductor substrate is determined utilizing the first luminescent intensity value and the second luminescent intensity value of the emitting layer. The thermal profile at least reflects information about one or more of the condition and the semiconductor substrate subsequent to exposure to the condition.

公开(公告)号：US09412691B2

公开(公告)日：2016-08-09

申请号：US14558782

申请日：2014-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heather M. Truax ,  Jared P. Yanofsky

IPC: G01R31/02 ,  H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  G01R31/28

CPC classification number: H01L23/49838 ,  G01R31/2863 ,  G01R31/2884 ,  G01R31/2886 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first surface, and wire bond pads on the first and second surfaces. The first surface also has a chip attach area with opening(s) that extends from the first surface to the second surface. A chip can be attached to the chip attach area and, because of the opening(s), wire bond pads on opposite sides (e.g., on the top and bottom) of the chip are accessible for testing. That is, wire bond pads on the first surface can be electrically connected to one side of the chip (e.g., to the top of the chip) and/or wire bond pads on the second surface can be electrically connected through the opening(s) to the opposite side of the chip (e.g., to the bottom of the chip).

Abstract translation: 披露的是芯片载体和使用它们的方法。 芯片载体各自包括具有第一表面的基部，与第一表面相对的第二表面，以及在第一和第二表面上的引线接合焊盘。 第一表面还具有带有从第一表面延伸到第二表面的开口的芯片附着区域。 芯片可以附接到芯片连接区域，并且由于开口，芯片的相对侧（例如，在顶部和底部）上的引线接合焊盘可访问以进行测试。 也就是说，第一表面上的引线接合焊盘可以电连接到芯片的一侧（例如，到芯片的顶部），和/或第二表面上的引线接合焊盘可以通过开口电连接， 到芯片的相对侧（例如，到芯片的底部）。