公开(公告)号：US20170263733A1

公开(公告)日：2017-09-14

申请号：US15608283

申请日：2017-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael GANZ ,  Bingwu LIU ,  Johannes Marinus VAN MEER ,  Sruthi MURALIDHARAN

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/3105

CPC classification number: H01L21/324 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/31055 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851 ,  H01L29/7854

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

公开(公告)号：US20150340501A1

公开(公告)日：2015-11-26

申请号：US14285042

申请日：2014-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  Johannes Marinus VAN MEER ,  Manfred ELLER ,  Vara Govindeswara Reddy VAKADA

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7855

Abstract: Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET.

Abstract translation: 公开了用于制造具有改善的沟道迁移率的独立栅极FinFET和所得到的器件的方法。 实施例可以包括在衬底上形成独立栅极鳍效应晶体管（FinFET）; 并在独立栅极FinFET的两个独立栅极之间的鳍内形成应力。

公开(公告)号：US20150115371A1

公开(公告)日：2015-04-30

申请号：US14519215

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael GANZ ,  Bingwu LIU ,  Johannes Marinus VAN MEER ,  Sruthi MURALIDHARAN

IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/324 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/31055 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851 ,  H01L29/7854

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

Abstract translation: 本发明提供一种形成半导体结构的方法，其包括：提供具有半导体衬底的中间半导体结构，具有与所述鳍的至少一部分接触的EG氧化物层的鳍和设置在所述鳍的一部分上的栅叠层 翅膀 在所述鳍片的不位于所述栅叠层下方的部分上形成氮化硅层; 并且在形成氮化硅层之后，在中间半导体结构上执行一个或多个离子注入步骤。 本发明还提供一种形成半导体结构的方法，包括：提供具有半导体衬底的中间半导体结构，具有与所述鳍的至少一部分接触的EG氧化物层的鳍和设置在所述鳍上的栅极材料; 在中间半导体结构的鳍和栅极材料之上形成包括氧化物层的栅堆叠硬掩模; 在栅堆叠硬掩模的氧化物层上形成氮化硅阻挡层; 执行一个或多个栅极堆叠硬掩模图案化步骤; 从不在闸门下方的翅片的部分去除EG氧化物层; 并且在从位于栅极下方的鳍片的部分去除EG氧化物层之后，执行一个或多个离子注入步骤。