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    Wafer stress control with backside patterning
    1.
    发明授权
    Wafer stress control with backside patterning 有权
    晶圆应力控制与背面图案化

    公开(公告)号：US09269607B2

    公开(公告)日：2016-02-23

    申请号：US14306598

    申请日：2014-06-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Edward Engbrecht ,  Donghun Kang ,  Rishikesh Krishnan ,  Oh-jung Kwon ,  Karen A. Nummy

    IPC: H01L21/30 ,  H01L21/762 ,  H01L21/308 ,  H01L21/321 ,  H01L29/06 ,  H01L21/66

    CPC classification number: H01L21/76227 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3212 ,  H01L22/12 ,  H01L29/0603 ,  H01L29/945

    Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.

    Abstract translation: 本发明的实施例提供了在制造期间控制半导体晶片中的应力的结构和方法。 诸如沟槽电容器的电路元件中使用的诸如深沟槽（DT）的特征赋予与DT的表面积成比例的晶片上的应力。 在实施例中，虚拟（非功能）DT的相应图案形成在晶片的背面，以抵消形成在晶片前侧上的电功能DT。 在一些实施例中，背面上的对应图案是与尺寸，布局和数量上的功能（前侧）图案相匹配的镜面图案。 通过在晶片的两侧形成次要图案，晶片正面和背面的应力平衡。 这有助于减少在晶圆制造过程中可能导致问题的翘曲等形貌问题。

    Asymmetric stressor DRAM
    2.
    发明授权
    Asymmetric stressor DRAM 有权
    不对称应力源DRAM

    公开(公告)号：US09240482B2

    公开(公告)日：2016-01-19

    申请号：US14476897

    申请日：2014-09-04

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ravi K. Dasaka ,  Shreesh Narasimha ,  Ahmed Nayaz Noemaun ,  Karen A. Nummy ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Bidan Zhang

    IPC: H01L21/00 ,  H01L29/78 ,  H01L27/108

    CPC classification number: H01L29/7848 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659

    Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

    Abstract translation: 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平坦化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。

    Semiconductor device including substrate contact and related method
    3.
    发明授权
    Semiconductor device including substrate contact and related method 有权
    包括衬底接触的半导体器件和相关方法

    公开(公告)号：US09412640B2

    公开(公告)日：2016-08-09

    申请号：US13749830

    申请日：2013-01-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Karen A. Nummy ,  Ravi M. Todi

    IPC: H01L21/44 ,  H01L21/74 ,  H01L29/94

    CPC classification number: H01L21/743 ,  H01L29/945

    Abstract: A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench;removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate.

    Abstract translation: 公开了一种在半导体器件上形成接触的方法。 所述方法包括：在所述半导体器件上形成掩模，所述掩模暴露设置在所述半导体器件的衬底中的沟槽内的至少一个接触节点; 在所述半导体器件上执行第一衬底接触蚀刻，所述第一衬底接触蚀刻凹陷所述沟槽内的所述暴露的接触节点; 去除设置在暴露的接触节点之上和沟槽的侧面上的一组节点膜; 以及在所述暴露的接触节点之上的所述沟槽内形成接触区域，所述接触区域接触所述衬底。

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