公开(公告)号：US10833160B1

公开(公告)日：2020-11-10

申请号：US16386363

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/82 ,  H01L21/033 ,  H01L21/027 ,  H01L21/306 ,  H01L29/417 ,  H01L27/088 ,  H01L29/40

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US10014364B1

公开(公告)日：2018-07-03

申请号：US15460914

申请日：2017-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Anthony Chou ,  Stephen Furkay ,  Naved Siddiqui

IPC: H01L49/02 ,  H01L21/3213 ,  H01L27/06 ,  H01L35/14 ,  H01L35/32

CPC classification number: H01L28/24 ,  H01L35/14 ,  H01L35/32

Abstract: Device structures and fabrication methods for an on-chip resistor. A first Seebeck terminal is arranged to overlap with first and second resistor bodies of the on-chip resistor. A second Seebeck terminal is also arranged to overlap with the first and second resistor bodies. The second Seebeck terminal has a spaced relationship with the first Seebeck terminal along a length of the first and second resistor bodies. The temperature coefficient of resistance of the on-chip resistor is based at least in part on a Seebeck coefficient of first and second Seebeck terminals.

公开(公告)号：US20200335591A1

公开(公告)日：2020-10-22

申请号：US16386363

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/311 ,  H01L21/033 ,  H01L29/40

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US10593555B2

公开(公告)日：2020-03-17

申请号：US15925928

申请日：2018-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qun Gao ,  Naved Siddiqui ,  Ankur Arya ,  John R Sporre

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/768 ,  H01L21/033 ,  H01L21/762 ,  H01L21/3105

Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.

公开(公告)号：US10256152B2

公开(公告)日：2019-04-09

申请号：US15657373

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Naved Siddiqui ,  Anthony I. Chou

IPC: H01L21/76 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10 ,  H01L29/417 ,  H01L27/092 ,  H01L27/088 ,  H01L27/12 ,  H01L21/762 ,  H01L21/8238

Abstract: One illustrative method disclosed herein includes, among other things, forming a conformal piezoelectric material liner layer on at least the opposing lateral sidewalls of a fin, forming a recessed layer of insulating material on opposite sides of the fin and on the conformal piezoelectric material liner layer, removing portions of the conformal piezoelectric material liner layer positioned above the recessed layer of insulating material to thereby expose a portion of the fin above the recessed upper surface, and forming a gate structure above the recessed layer of insulating material and around a portion of the fin positioned above the recessed upper surface.

公开(公告)号：US20190027601A1

公开(公告)日：2019-01-24

申请号：US15657373

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Naved Siddiqui ,  Anthony I. Chou

IPC: H01L29/78 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes, among other things, forming a conformal piezoelectric material liner layer on at least the opposing lateral sidewalls of a fin, forming a recessed layer of insulating material on opposite sides of the fin and on the conformal piezoelectric material liner layer, removing portions of the conformal piezoelectric material liner layer positioned above the recessed layer of insulating material to thereby expose a portion of the fin above the recessed upper surface, and forming a gate structure above the recessed layer of insulating material and around a portion of the fin positioned above the recessed upper surface.