公开(公告)号：US10833160B1

公开(公告)日：2020-11-10

申请号：US16386363

申请日：2019-04-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/82 ,  H01L21/033 ,  H01L21/027 ,  H01L21/306 ,  H01L29/417 ,  H01L27/088 ,  H01L29/40

摘要： Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US10269654B1

公开(公告)日：2019-04-23

申请号：US15890246

申请日：2018-02-06

申请人： GLOBALFOUNDRIES INC.

发明人： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

摘要： At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10204797B1

公开(公告)日：2019-02-12

申请号：US15890210

申请日：2018-02-06

申请人： GLOBALFOUNDRIES INC.

发明人： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Jessica Dechene ,  Haigou Huang

IPC分类号： H01L21/00 ,  H01L21/3105 ,  H01L21/02 ,  C23C16/36 ,  H01L21/67 ,  C23C16/56 ,  C23C16/26

摘要： The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.

公开(公告)号：US10453751B2

公开(公告)日：2019-10-22

申请号：US15432016

申请日：2017-02-14

申请人： GLOBALFOUNDRIES INC.

发明人： Xiaofeng Qiu ,  Michael V. Aquilino ,  Patrick D. Carpenter ,  Jessica Dechene ,  Ming Hao Tang ,  Haigou Huang ,  Huy Cao

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L23/535 ,  H01L21/768 ,  H01L29/423 ,  H01L27/088 ,  H01L21/033 ,  H01L21/311 ,  H01L29/417

摘要： A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.

公开(公告)号：US20200335591A1

公开(公告)日：2020-10-22

申请号：US16386363

申请日：2019-04-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L21/311 ,  H01L21/033 ,  H01L29/40

摘要： Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US10325819B1

公开(公告)日：2019-06-18

申请号：US15920303

申请日：2018-03-13

申请人： GLOBALFOUNDRIES INC.

发明人： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3105

摘要： At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.