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    FULLY ALIGNED VIA IN GROUND RULE REGION
    2.
    发明申请
    FULLY ALIGNED VIA IN GROUND RULE REGION 审中-公开

    公开(公告)号：US20190088541A1

    公开(公告)日：2019-03-21

    申请号：US15709956

    申请日：2017-09-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nicholas V. LICAUSI ,  Xunyuan ZHANG

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L21/76883 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53295

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

    SELF ALIGNED BURIED POWER RAIL
    4.
    发明申请
    SELF ALIGNED BURIED POWER RAIL 审中-公开

    公开(公告)号：US20200006112A1

    公开(公告)日：2020-01-02

    申请号：US16568902

    申请日：2019-09-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nicholas V. LICAUSI ,  Guillaume BOUCHE ,  Lars W. LIEBMANN

    IPC: H01L21/74 ,  H01L27/108 ,  H01L27/088 ,  H01L27/092

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

    FULLY ALIGNED VIA IN GROUND RULE REGION
    5.
    发明申请
    FULLY ALIGNED VIA IN GROUND RULE REGION 审中-公开

    公开(公告)号：US20190311948A1

    公开(公告)日：2019-10-10

    申请号：US16436117

    申请日：2019-06-10

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nicholas V. LICAUSI ,  Xunyuan ZHANG

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

    SELF ALIGNED BURIED POWER RAIL
    6.
    发明申请
    SELF ALIGNED BURIED POWER RAIL 审中-公开

    公开(公告)号：US20180294267A1

    公开(公告)日：2018-10-11

    申请号：US15481826

    申请日：2017-04-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nicholas V. LICAUSI ,  Guillaume BOUCHE ,  Lars W. LIEBMANN

    IPC: H01L27/108 ,  H01L27/088 ,  H01L27/092 ,  H01L21/74

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

    FINFET FIN HEIGHT CONTROL
    7.
    发明申请
    FINFET FIN HEIGHT CONTROL 有权
    FINFET高度控制

    公开(公告)号：US20140306317A1

    公开(公告)日：2014-10-16

    申请号：US13862819

    申请日：2013-04-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nicholas V. LICAUSI

    IPC: H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L21/311

    CPC classification number: H01L21/30625 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

    Abstract: Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin structures may be selectively removed after treatment to increase its mechanical strength such as by, for example, annealing and curing. A sacrificial material may be deposited over the isolation material between the fin structures in a substantially uniform thickness. The top portion of the fin structures may be selectively removed to achieve a uniform planar surface over the fin structures and sacrificial material. The sacrificial material may then be selectively removed to achieve a uniform fin height relative to the isolation material.

    Abstract translation: 公开了FinFET制造的翅片高度控制技术。 该技术包括一种用于控制多个翅片结构的高度以实现其相对于位于半导体衬底上的翅片结构之间的隔离材料的顶表面的均匀高度的方法。 位于翅片结构之间的隔离材料可以在处理之后选择性地除去以增加其机械强度，例如通过退火和固化。 牺牲材料可以以基本均匀的厚度沉积在翅片结构之间的隔离材料上。 可以选择性地去除翅片结构的顶部以在翅片结构和牺牲材料上实现均匀的平坦表面。 然后可以选择性地去除牺牲材料以实现相对于隔离材料的均匀的翅片高度。

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