公开(公告)号：US10340142B1

公开(公告)日：2019-07-02

申请号：US15919119

申请日：2018-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jiehui Shu ,  Pei Liu ,  Jinping Liu

IPC: H01L21/033 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213

Abstract: At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.

公开(公告)号：US10460986B2

公开(公告)日：2019-10-29

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US10325819B1

公开(公告)日：2019-06-18

申请号：US15920303

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3105

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10930549B2

公开(公告)日：2021-02-23

申请号：US16573209

申请日：2019-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US20190280114A1

公开(公告)日：2019-09-12

申请号：US15919079

申请日：2018-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Xusheng Wu ,  Haigou Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US10269654B1

公开(公告)日：2019-04-23

申请号：US15890246

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10204797B1

公开(公告)日：2019-02-12

申请号：US15890210

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Jessica Dechene ,  Haigou Huang

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/02 ,  C23C16/36 ,  H01L21/67 ,  C23C16/56 ,  C23C16/26

Abstract: The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.