公开(公告)号：US09536870B2

公开(公告)日：2017-01-03

申请号：US14977737

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/06 ,  G06F17/50 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L27/0262 ,  G06F17/5063 ,  G06F17/5072 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66121 ,  H01L29/66393 ,  H01L29/7408 ,  H01L29/7412 ,  H01L29/742 ,  H01L29/7436 ,  H01L29/861

Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.

Abstract translation: 公开了一种静电放电保护电路。 一种制造半导体结构的方法包括在n阱中形成包括n阱体接触和阳极之间的第一多个指状物的半导体可控整流器，以及p阱体接触件和 阴极在p阱中。

公开(公告)号：US09461149B2

公开(公告)日：2016-10-04

申请号：US14484916

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongmei Li ,  Junjun Li ,  Xiaoping Liang ,  Kai Zhao

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers.

Abstract translation: 提供了制造具有降低的栅极电阻的堆叠的纳米线场效应晶体管（FET）的方法。 可以通过首先形成交替的牺牲材料层和纳米线材料层的材料堆叠来提供堆叠的纳米线FET中的纳米线堆叠。 随后去除材料堆叠中的牺牲材料层和选定的纳米线材料层以增加两个活性纳米线材料层之间的垂直距离。

公开(公告)号：US09287178B2

公开(公告)日：2016-03-15

申请号：US13632237

申请日：2012-10-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongmei Li ,  Junjun Li

IPC: H01L21/20 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.

Abstract translation: 本公开的方面提供了形成在包括隔离鳍片的块状衬底上的多栅极场效应晶体管（FET）及其形成方法。 在一个实施例中，多栅极FET包括：形成在本体衬底上的多个硅鳍结构，每个硅鳍结构包括体区，源区和漏区; 其中每个硅鳍结构的主体区域的底部部分包括将本体区域与本体衬底隔离的倾斜形状，并且其中所述多个硅鳍结构体经由所述源极区域的至少一部分附接到所述本体衬底， 或至少一部分漏极区域，或两者。

公开(公告)号：US09263402B2

公开(公告)日：2016-02-16

申请号：US14554643

申请日：2014-11-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li

IPC: H01L21/00 ,  H01L23/60 ,  H01L27/02 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L23/60 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.

公开(公告)号：US09236398B2

公开(公告)日：2016-01-12

申请号：US14513709

申请日：2014-10-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

IPC: H01L29/66 ,  H01L21/338 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/7624 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

Abstract: Device structures and design structures for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract translation: 无源器件的器件结构和设计结构，可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

公开(公告)号：US09413169B2

公开(公告)日：2016-08-09

申请号：US14243295

申请日：2014-04-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H02H9/042

Abstract: Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.

Abstract translation: 提供静电放电保护的电路和方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，被配置为选择性地将定时电路的节点与电源钳位装置连接的传输门，以及 控制电路与节点耦合。 控制电路被配置为基于电容器是否有缺陷来控制传输门。 如果定时电路中的电容器有故障并且相关的芯片被供电，则定时电路可以被去激活。 或者，如果定时电路中的电容器没有故障，则定时电路可以被激活。

公开(公告)号：US09954002B2

公开(公告)日：2018-04-24

申请号：US15040307

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongmei Li ,  Junjun Li

IPC: H01L27/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.

公开(公告)号：US20160197080A1

公开(公告)日：2016-07-07

申请号：US15067307

申请日：2016-03-11

Applicant: GlobalFoundries Inc.

Inventor： John B. Campi, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Souvick Mitra ,  Mujahid Muhammad

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0928 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816 ,  H01L29/7835

Abstract: Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.

公开(公告)号：US09575115B2

公开(公告)日：2017-02-21

申请号：US13649699

申请日：2012-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nathaniel R. Chadwick ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Kirk D. Peterson ,  Andrew A. Turner

IPC: G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2872 ,  G01R31/2831 ,  G01R31/2894 ,  H01L22/14 ,  H01L22/20

Abstract: A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device.

Abstract translation: 一种系统和方法对集成电路器件进行排序。 根据使用制造设备的集成电路设计，在晶片上制造集成电路器件。 该设计生产的集成电路器件根据制造工艺变化相同设计和执行不同。 集成电路设备在使用时可用于一系列环境条件。 在集成电路器件上进行测试。 每个设备单独预测环境最大值。 环境最大值包括每个设备在给定故障率以上执行时不得超过的环境条件。 基于为每个设备预测的环境最大值，为每个集成电路设备分配多个等级中的至少一个。 基于分配给每个设备的等级，将集成电路设备提供给具有不同环境条件的不同服务形式。

公开(公告)号：US09425185B2

公开(公告)日：2016-08-23

申请号：US14290141

申请日：2014-05-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  You Li ,  Souvick Mitra

IPC: H02H9/00 ,  H01L27/02 ,  H01L23/525 ,  H01G17/00 ,  H01G13/00

CPC classification number: H01L27/0266 ,  H01G13/00 ,  H01G17/00 ,  H01L23/5256 ,  H01L27/0285 ,  H01L2924/0002 ,  Y10T29/435 ,  H01L2924/00

Abstract: Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, and a power clamp device coupled with the timing circuit at the node. The capacitor includes a plurality of capacitor elements. The protection circuit further includes a plurality of electronic fuses. Each electronic fuse is coupled with a respective one of the capacitor elements. A field effect transistor may be coupled in parallel with the resistor of the timing circuit, and may be used to bypass the resistor to provide a programming current to any electronic fuse coupled with a capacitor element of abnormally low impedance.

Abstract translation: 制造提供静电放电保护的电路的电路和方法，以及保护集成电路免受静电放电的方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，以及与节点处的定时电路耦合的功率钳位装置。 电容器包括多个电容器元件。 保护电路还包括多个电子保险丝。 每个电子熔断器与相应的一个电容器元件耦合。 场效应晶体管可以与定时电路的电阻并联耦合，并且可以用于旁路电阻器以向与异常低阻抗的电容器元件耦合的任何电子熔丝提供编程电流。