公开(公告)号：US10224396B1

公开(公告)日：2019-03-05

申请号：US15817629

申请日：2017-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Daisy Vaughn ,  Thai Doan

IPC: H01L29/00 ,  H01L29/06 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to deep trench isolation structures and methods of manufacture. The structure includes: at least one gate structure on a substrate; an interlevel dielectric material above the substrate; and a trench isolation structure extending into the substrate adjacent to the at least one gate structure and terminating in the interlevel dielectric material above the substrate.

公开(公告)号：US20170069518A1

公开(公告)日：2017-03-09

申请号：US14845896

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brett Cucci ,  Thai Doan ,  Jeffrey P. Gambino ,  Rebecca K. Kelley ,  Jed H. Rankin ,  Daniel S. Vanslette

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/6831 ,  H01L21/68735 ,  H01L21/68757 ,  H01L21/76898

Abstract: An apparatus and method of etching. The apparatus including a support substrate having a top surface; a stack of a multiplicity of layers formed on the top surface of the support substrate from a lowermost layer on the top surface of the support substrate to a topmost layer that is furthest from the support substrate; and wherein an entirety of the top surface of the topmost layer is not planar and at least one of the multiplicity of layers that is not the topmost layer is an electrically conductive layer.

Abstract translation: 蚀刻装置和方法。 该装置包括具有顶表面的支撑衬底; 从支撑基板的顶表面上的最下层到距离支撑基板最远的最上层，形成在支撑基板的顶表面上的多个层的堆叠; 并且其中最顶层的顶表面的整体不是平面的，并且不是最上层的多个层中的至少一个是导电层。

公开(公告)号：US09922973B1

公开(公告)日：2018-03-20

申请号：US15611184

申请日：2017-06-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Thai Doan

IPC: H01L21/76 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/764 ,  H01L21/02 ,  H01L21/763

CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L21/763 ,  H01L21/764 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/1095

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods of manufacture. The structure includes a bulk substrate with a fully depleted region below source and drain regions of at least one gate stack and confined by deep trench isolation structures lined with doped material.