公开(公告)号：US09443764B2

公开(公告)日：2016-09-13

申请号：US14052366

申请日：2013-10-11

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jeffrey C. Maling ,  Anthony K. Stamper ,  Zeljka Topic-Beganovic ,  Daniel S. Vanslette

IPC: H01L21/768 ,  H05K1/11 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K1/115 ,  H01L2924/00

Abstract: A method and structure for eliminating through silicon via poor reveal is disclosed. In one embodiment, the method includes obtaining a wafer having a front side, a back side and partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side. A region of the back side of the wafer is patterned and etched to expose and reveal a portion of each of the plurality of through silicon vias. A metal layer is deposited on the back side of the wafer to form a back side metallization. The metal layer covers all of the back side including the etched region of the back side and the exposed portions of each of the through silicon vias.

Abstract translation: 公开了一种通过不良露出来消除硅的方法和结构。 在一个实施例中，该方法包括获得具有正面，背面以及通过硅通孔部分蚀刻和金属化的晶片，每个硅通孔从前侧的一部分延伸穿过后侧的一部分，在到达 背面。 对晶片的背面的区域进行图案化和蚀刻，以暴露和显露多个通孔中的每个通孔的一部分。 金属层沉积在晶片的背面以形成背面金属化。 金属层覆盖包括后侧的蚀刻区域和通孔硅通孔中的每一个的暴露部分的所有背面。

公开(公告)号：US20170069518A1

公开(公告)日：2017-03-09

申请号：US14845896

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brett Cucci ,  Thai Doan ,  Jeffrey P. Gambino ,  Rebecca K. Kelley ,  Jed H. Rankin ,  Daniel S. Vanslette

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/6831 ,  H01L21/68735 ,  H01L21/68757 ,  H01L21/76898

Abstract: An apparatus and method of etching. The apparatus including a support substrate having a top surface; a stack of a multiplicity of layers formed on the top surface of the support substrate from a lowermost layer on the top surface of the support substrate to a topmost layer that is furthest from the support substrate; and wherein an entirety of the top surface of the topmost layer is not planar and at least one of the multiplicity of layers that is not the topmost layer is an electrically conductive layer.

Abstract translation: 蚀刻装置和方法。 该装置包括具有顶表面的支撑衬底; 从支撑基板的顶表面上的最下层到距离支撑基板最远的最上层，形成在支撑基板的顶表面上的多个层的堆叠; 并且其中最顶层的顶表面的整体不是平面的，并且不是最上层的多个层中的至少一个是导电层。

公开(公告)号：US09390969B2

公开(公告)日：2016-07-12

申请号：US14600273

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： David A. DeMuynck ,  Zhong-Xiang He ,  Daniel R. Miga ,  Matthew D. Moon ,  Daniel S. Vanslette ,  Eric J. White

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

Abstract translation: 本公开一般涉及集成电路（IC），IC互连及其制造方法，更具体地，涉及高性能电感器。 IC包括设置在基板上的电介质层内的至少一个沟槽。 沟槽被保形地涂覆有衬里和种子层，并且包括内部的互连。 互连包括在互连的侧壁上的硬掩模。