公开(公告)号：US09519502B2

公开(公告)日：2016-12-13

申请号：US14548624

申请日：2014-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guy L. Guthrie ,  Naresh Nayar ,  Geraint North ,  William J. Starke ,  Albert J. Van Norstrand, Jr.

IPC: G06F12/08 ,  G06F12/12 ,  G06F11/14 ,  G06F9/455

CPC classification number: G06F9/45558 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1438 ,  G06F11/1458 ,  G06F11/1484 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2046 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0833 ,  G06F12/0855 ,  G06F12/128 ,  G06F2009/45583 ,  G06F2201/86 ,  G06F2212/151 ,  G06F2212/62 ,  G06F2212/621

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines, a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, periodically check the image modification flags and write only the memory address of the flagged cache rows in the defined log. The processor unit is further arranged to monitor the free space available in the defined log and to trigger an interrupt if the free space available falls below a specific amount.

Abstract translation: 计算机系统包括处理器单元，其被配置为运行运行一个或多个虚拟机的管理程序，连接到处理器单元并包括多个高速缓存行的高速缓存，每个高速缓存行包括存储器地址，高速缓存行和图像修改标志 以及连接到高速缓存并被布置成存储至少一个虚拟机的图像的存储器。 处理器单元被布置为在存储器中定义日志，并且高速缓存还包括高速缓存控制器，其被布置为设置由被备份的虚拟机修改的高速缓存行的映像修改标志，周期性地检查映像修改标志，并且仅写入 定义的日志中标记的缓存行的内存地址。 处理器单元还被布置成监视定义的日志中可用的可用空间，并且如果可用空间低于特定量，则触发中断。

公开(公告)号：US09244725B2

公开(公告)日：2016-01-26

申请号：US14037923

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0828

Abstract: In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.

Abstract translation: 在具有处理器核心和包括支持处理器核心的高速缓冲存储器的共享存储器系统的数据处理系统中，处理器核心响应于执行正在执行的存储器事务中的存储器访问指令执行事务存储器访问请求 由处理器核心。 响应于接收事务存储器访问请求，缓存存储器的调度逻辑评估用于调度的事务存储器访问请求，其中评估包括确定存储器事务是否具有故障事务状态。 响应于确定存储器事务具有失败的事务状态，分派逻辑不会缓存高速缓冲存储器的服务存储器访问请求，并且至少响应于事务存储器访问请求更新缓存存储器的替换顺序信息 。

公开(公告)号：US09244724B2

公开(公告)日：2016-01-26

申请号：US13967795

申请日：2013-08-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0828

Abstract: In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.

公开(公告)号：US09367348B2

公开(公告)日：2016-06-14

申请号：US13967853

申请日：2013-08-15

Applicant: GLOBALFOUNDRIES INC

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Jonathan R. Jackson ,  Derek E. Williams

IPC: G06F12/12 ,  G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F12/0802 ,  G06F12/0815 ,  G06F12/0864 ,  G06F12/123

Abstract: A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

Abstract translation: 处理单元包括处理器核和高速缓冲存储器。 高速缓冲存储器中的条目被分组在多个同余类中。 高速缓冲存储器包括跟踪逻辑，其跟踪事务占用，包括由存储器事务的事务存储器访问请求访问的高速缓存行。 高速缓冲存储器响应于接收指定具有映射到同余类的目标地址的目标高速缓存行的存储器访问请求，形成包含事务占用空间内的高速缓存行的一致性类中的一组工作方式，并更新 一致类中缓存行的替换顺序。 基于工作集中的至少一个高速缓存行的成员身份，该更新将至少一个不是目标高速缓存行的高速缓存行促进到其中至少一个高速缓存行不太可能被替换的替换顺序位置。