公开(公告)号：US09171764B2

公开(公告)日：2015-10-27

申请号：US14106347

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ryan Ryoung Han Kim ,  Jason Cantone

IPC: H01L21/311 ,  H01L21/8238 ,  H01L27/11 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/845 ,  H01L27/1104 ,  H01L29/66795

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 在一个实施例中，制造集成电路的方法包括蚀刻上心轴层以形成上心轴。 至少一个上心轴具有第一临界尺寸，并且至少一个上心轴具有不等于第一临界尺寸的第二临界尺寸。 该方法还包括在上心轴上形成上间隔件并使用上间隔件作为蚀刻掩模蚀刻下心轴层以形成下心轴。 该方法还包括形成邻近下心轴的下间隔件，并使用下间隔件蚀刻材料作为蚀刻掩模以形成可变间隔的结构。

公开(公告)号：US10283505B2

公开(公告)日：2019-05-07

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/52 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L23/528 ,  H01L21/02 ,  H01L21/321 ,  H01L27/02 ,  H01L29/49

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US09595478B2

公开(公告)日：2017-03-14

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US20150170973A1

公开(公告)日：2015-06-18

申请号：US14106347

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ryan Ryoung Han Kim ,  Jason Cantone

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L27/11

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/845 ,  H01L27/1104 ,  H01L29/66795

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 在一个实施例中，制造集成电路的方法包括蚀刻上心轴层以形成上心轴。 至少一个上心轴具有第一临界尺寸，并且至少一个上心轴具有不等于第一临界尺寸的第二临界尺寸。 该方法还包括在上心轴上形成上间隔件并使用上间隔件作为蚀刻掩模蚀刻下心轴层以形成下心轴。 该方法还包括形成邻近下心轴的下间隔件，并使用下间隔件蚀刻材料作为蚀刻掩模以形成可变间隔的结构。