公开(公告)号：US09653571B2

公开(公告)日：2017-05-16

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

公开(公告)号：US09496257B2

公开(公告)日：2016-11-15

申请号：US14318822

申请日：2014-06-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Soon-cheon Seo ,  Linus Jang

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/027 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L21/30604 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

Abstract translation: 在衬底上形成半导体材料部分和栅极结构之后，在半导体材料部分和栅极结构上沉积介电材料层。 在电介质材料层上进行各向异性蚀刻以形成栅极间隔物，而掩模层保护半导体材料部分和栅极结构的外围部分以避免半导体表面的不期望的物理暴露。 可以进行选择性外延以在半导体材料部分上形成凸起的有源区。 通过介电材料层可以防止选择性外延期间的半导体生长缺陷的形成。 或者，可以在覆盖半导体材料部分的栅极结构上形成介电栅极间隔物之后执行选择性半导体沉积工艺。 半导体生长缺陷可以通过蚀刻去除，而掩模层保护半导体材料部分上的凸起的有源区。

公开(公告)号：US09209038B2

公开(公告)日：2015-12-08

申请号：US14267959

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/823431

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 一种用于制造集成电路的示例性方法包括提供具有第一和第二区域并且包括上部和下部心轴层的可图案化结构。 该方法在第一和第二区域中从上心轴层蚀刻上心轴。 该方法包括形成在第一区域中具有与上心轴相邻的第一宽度的第一上间隔结构，并且形成第二上间隔结构，其具有不等于第二区中相邻上心轴的第一宽度的第二宽度。 该方法使用第一和第二上间隔结构蚀刻下心轴层作为蚀刻掩模以形成下心轴。 此外，该方法包括形成邻近下心轴的间隔物，并使用间隔物蚀刻材料作为蚀刻掩模以形成可变间隔的特征。

公开(公告)号：US08716094B1

公开(公告)日：2014-05-06

申请号：US13682769

申请日：2012-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Seo Park ,  Linus Jang ,  Jin Cho

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/311

CPC classification number: H01L29/66742 ,  H01L29/66795

Abstract: Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.

Abstract translation: 提供了使用双重图案记忆技术形成FinFET器件的方法。 具体来说，首先将通过限定一组翅片，沉积多晶硅层和沉积硬掩模来形成器件。 此后，将执行线的前端（FEOL）光刻蚀刻，光刻蚀刻（LELE）处理以在器件中形成一组沟槽。 该组沟槽将填充随后抛光的氧化物层。 此后，选择性地蚀刻器件以产生（例如，多晶硅）栅极图案。

公开(公告)号：US20160064236A1

公开(公告)日：2016-03-03

申请号：US14935767

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask.

Abstract translation: 一种方法包括在半导体衬底上形成材料层并执行第一侧壁图像转移工艺以在材料层之上形成第一多个间隔物和第二多个间隔物，其中第一和第二多个间隔物位于 相应的半导体衬底的第一和第二区域，并且具有相同的初始宽度和相同的间距间距。 在材料层的上方形成掩模层，以便覆盖第一多个间隔物并露出第二多个间隔物，并且通过暴露的第二多个间隔物上的掩模层进行第一蚀刻工艺，从而形成 多个宽度窄于所述初始宽度的宽度窄的间隔物，其中所述第一多个间隔物和所述多个减小宽度的间隔物限定蚀刻掩模。

公开(公告)号：US09214360B2

公开(公告)日：2015-12-15

申请号：US13874577

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract translation: 本文公开了具有不同宽度的图案特征的方法。 在一个示例中，该方法包括在半导体衬底之上形成材料层，在材料层之上形成掩模层，其中掩模层由位于半导体衬底的第一区域上方的第一多个特征构成，第二 多个特征位于所述半导体衬底的第二区域之上，其中所述第一和第二多个特征具有相同的间距间距，并且其中所述第一和第二多个特征具有不同的宽度，并且对所述第一和第二多个特征层进行至少一个蚀刻处理 材料通过掩模层。

公开(公告)号：US09209037B2

公开(公告)日：2015-12-08

申请号：US14196931

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Jin Cho ,  Ryan Ryoung-Han Kim

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底的选定区域中形成鳍结构。 该方法包括用掩模覆盖翅片结构和半导体衬底，并在掩模中形成沟槽，以在所选择的区域中限定不超过两个暴露的翅片结构。 此外，该方法包括去除暴露的翅片结构以向选定区域提供所需数量的翅片结构。

公开(公告)号：US20140273443A1

公开(公告)日：2014-09-18

申请号：US13834946

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC. ,  RENESAS ELECTRONICS CORPORATION ,  INTERNATIONL BUSINESS MACHINES CORPORATION

Inventor： Linus Jang ,  Yoshinori Matsui ,  Chiahsun Tseng

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括形成绝缘材料层，在绝缘材料层之上形成图案化的光致抗蚀剂层，其中所述图案化的光致抗蚀剂层具有限定在其中的开口，在图案化层中的开口内形成内部间隔物 光致抗蚀剂，其中间隔物限定尺寸较小的开口，通过绝缘材料层上的尺寸减小的开口执行蚀刻工艺，以在绝缘材料层中限定沟槽/孔型特征，并在该层中形成导电结构 绝缘材料层中的沟槽/孔型特征。

公开(公告)号：US09653573B2

公开(公告)日：2017-05-16

申请号：US14827510

申请日：2015-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US09595478B2

公开(公告)日：2017-03-14

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。