公开(公告)号：US09570344B2

公开(公告)日：2017-02-14

申请号：US14752210

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal Kamineni ,  Nicholas Vincent Licausi ,  Shariq Siddiqui ,  Jeremy Austin Wahl

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76814 ,  H01L23/535

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract translation: 一种方法可以包括在半导体结构中形成接触沟槽，使得接触沟槽延伸到接触层，形成包括使用硬掩模层，并用牺牲材料层填充接触沟槽，牺牲材料层形成在触点上 形成。 半导体结构可以包括在接触层上的牺牲材料层。

公开(公告)号：US09508712B2

公开(公告)日：2016-11-29

申请号：US14146075

申请日：2014-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jeremy Austin Wahl ,  Nicholas Vincent LiCausi

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/34 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L23/345 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions.

Abstract translation: 公开了纳米线器件，其包括第一和第二纳米线，围绕第一和第二纳米线的一部分定位的栅极结构以及围绕器件的源极/漏极区域中的第一纳米线的至少一部分的相变材料，但不包括 围绕源极/漏极区域中的第二纳米线。

公开(公告)号：US10395981B2

公开(公告)日：2019-08-27

申请号：US15793253

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Jeremy Austin Wahl

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/04

Abstract: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.

公开(公告)号：US20190122921A1

公开(公告)日：2019-04-25

申请号：US15793253

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Jeremy Austin Wahl

IPC: H01L21/768 ,  H01L29/04

CPC classification number: H01L21/76822 ,  H01L21/28052 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/045 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.

公开(公告)号：US20150187762A1

公开(公告)日：2015-07-02

申请号：US14146075

申请日：2014-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jeremy Austin Wahl ,  Nicholas Vincent LiCausi

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/34 ,  H01L23/525 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L23/345 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions.

Abstract translation: 公开了纳米线器件，其包括第一和第二纳米线，围绕第一和第二纳米线的一部分定位的栅极结构以及围绕器件的源极/漏极区域中的第一纳米线的至少一部分的相变材料，但不包括 围绕源极/漏极区域中的第二纳米线。