公开(公告)号：US20170316944A1

公开(公告)日：2017-11-02

申请号：US15646570

申请日：2017-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chi Dong Nguyen ,  Klaus Hempel

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device has an active region that includes a semiconductor layer. A transistor is formed in and above the active region, wherein the transistor has an implanted halo region that includes a halo dopant species and defines a halo dopant profile in the semiconductor layer. An implanted carbon species is positioned in the semiconductor layer, wherein the implanted carbon species defines a carbon species profile in the semiconductor layer that is substantially the same as the halo dopant profile of the implanted halo region in the semiconductor layer.

公开(公告)号：US10121665B2

公开(公告)日：2018-11-06

申请号：US15646570

申请日：2017-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chi Dong Nguyen ,  Klaus Hempel

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device has an active region that includes a semiconductor layer. A transistor is formed in and above the active region, wherein the transistor has an implanted halo region that includes a halo dopant species and defines a halo dopant profile in the semiconductor layer. An implanted carbon species is positioned in the semiconductor layer, wherein the implanted carbon species defines a carbon species profile in the semiconductor layer that is substantially the same as the halo dopant profile of the implanted halo region in the semiconductor layer.

公开(公告)号：US09917016B2

公开(公告)日：2018-03-13

申请号：US14567544

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Klaus Hempel ,  Dina Triyoso

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/823828 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.

公开(公告)号：US20130017679A1

公开(公告)日：2013-01-17

申请号：US13624235

申请日：2012-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Markus Lenski ,  Klaus Hempel ,  Vivien Schroeder ,  Robert Binder ,  Joachim Metzger

IPC: H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure.

Abstract translation: 通常，本公开涉及高k金属栅电极结构中的功函数调整。 在一个说明性实施例中，公开了一种方法，其包括移除第一栅极电极结构和第二栅电极结构的占位符材料，以及在第一和第二栅电极结构中形成第一功函数调节材料层，其中第一工件 功能调整材料层包括氮化钽层。 该方法还包括通过使用氮化钽层作为蚀刻停止层从第二栅极电极结构去除第一功函数调整材料层的一部分，通过执行湿化学蚀刻工艺去除氮化钽层，以及形成第二 第二栅电极结构中的功函数调整材料层，以及第一栅电极结构中的第一功函数调整材料层的未除去部分之上。

公开(公告)号：US08735270B2

公开(公告)日：2014-05-27

申请号：US13888753

申请日：2013-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Klaus Hempel ,  Sven Beyer ,  Markus Lenski ,  Stephan Kruegel

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28026 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7843

Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract translation: 在替代浇口方法中，可以通过在去除占位材料的中间状态下进行材料侵蚀过程来实现闸门开口的优越的横截面形状。 因此，当执行拐角舍入处理顺序时，占位符材料的剩余部分可以有效地保护诸如高k电介质材料的底层敏感材料。

公开(公告)号：US09735012B2

公开(公告)日：2017-08-15

申请号：US14667778

申请日：2015-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chi Dong Nguyen ,  Klaus Hempel

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/3205 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method of forming a semiconductor device is provided including co-implanting a halo species and carbon in a semiconductor layer with a finite tilt angle with respect to a direction perpendicular to the surface of the semiconductor layer. Furthermore, a semiconductor device is provided including an N-channel transistor comprising a halo region made of a halo species with a dopant profile formed in a semiconductor layer and a carbon species implanted in the semiconductor layer with substantially the same dopant profile as the dopant profile of the halo region.

公开(公告)号：US20160284549A1

公开(公告)日：2016-09-29

申请号：US14667778

申请日：2015-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chi Dong Nguyen ,  Klaus Hempel

IPC: H01L21/225 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method of forming a semiconductor device is provided including co-implanting a halo species and carbon in a semiconductor layer with a finite tilt angle with respect to a direction perpendicular to the surface of the semiconductor layer. Furthermore, a semiconductor device is provided including an N-channel transistor comprising a halo region made of a halo species with a dopant profile formed in a semiconductor layer and a carbon species implanted in the semiconductor layer with substantially the same dopant profile as the dopant profile of the halo region.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体层中相对于与半导体层的表面垂直的方向具有有限倾斜角共同注入卤素物质和碳。 此外，提供了一种半导体器件，其包括N沟道晶体管，该N沟道晶体管包括由在半导体层中形成的掺杂剂分布的卤素物质形成的卤素区域，并且注入到半导体层中的碳物质具有与掺杂剂分布基本相同的掺杂剂分布 的光晕区域。

公开(公告)号：US20160172251A1

公开(公告)日：2016-06-16

申请号：US14567544

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Klaus Hempel ,  Dina Triyoso

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.

Abstract translation: 提供了集成电路及其形成方法。 形成集成电路的示例性方法包括形成覆盖半导体衬底的虚拟栅极结构。 虚拟栅极结构包括栅极介电层，虚拟栅极层，蚀刻停止层和虚拟栅极覆盖层。 在虚拟栅极结构的侧壁附近形成第一侧壁间隔物。 源极和漏极区域形成在与第一侧壁间隔物相邻的半导体衬底中。 电介质材料沉积在第一侧壁间隔物附近。 在沉积介电材料之后，用选择性的第一蚀刻剂来蚀刻伪栅极盖层。 蚀刻停止层用对其选择的第二蚀刻剂进行蚀刻。 蚀刻虚拟栅极层以形成栅极凹槽，并且栅极材料沉积在栅极凹部中。

公开(公告)号：US20130273729A1

公开(公告)日：2013-10-17

申请号：US13888753

申请日：2013-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Klaus Hempel ,  Sven Beyer ,  Markus Lenski ,  Stephan Kruegel

IPC: H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28026 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7843

Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract translation: 在替代浇口方法中，可以通过在去除占位材料的中间状态下进行材料侵蚀过程来实现闸门开口的优越的横截面形状。 因此，当执行拐角舍入处理顺序时，占位符材料的剩余部分可以有效地保护诸如高k电介质材料的底层敏感材料。

公开(公告)号：US08440559B2

公开(公告)日：2013-05-14

申请号：US13624235

申请日：2012-09-21

Applicant: Globalfoundries Inc.

Inventor： Markus Lenski ,  Klaus Hempel ,  Vivien Schroeder ,  Robert Binder ,  Joachim Metzger

IPC: H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure.

Abstract translation: 通常，本公开涉及高k金属栅电极结构中的功函数调整。 在一个说明性实施例中，公开了一种方法，其包括移除第一栅极电极结构和第二栅电极结构的占位符材料，以及在第一和第二栅电极结构中形成第一功函数调节材料层，其中第一工件 功能调整材料层包括氮化钽层。 该方法还包括通过使用氮化钽层作为蚀刻停止层从第二栅极电极结构去除第一功函数调整材料层的一部分，通过执行湿化学蚀刻工艺去除氮化钽层，以及形成第二 第二栅电极结构中的功函数调整材料层，以及第一栅电极结构中的第一功函数调整材料层的未除去部分之上。