公开(公告)号：US20200083102A1

公开(公告)日：2020-03-12

申请号：US16685648

申请日：2019-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. STEPHENS ,  Daniel CHANEMOUGAME ,  Ruilong XIE ,  Lars W. LIEBMANN ,  Gregory A. NORTHROP

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US20190214298A1

公开(公告)日：2019-07-11

申请号：US15868479

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. STEPHENS ,  Daniel CHANEMOUGAME ,  Ruilong XIE ,  Lars W. LIEBMANN ,  Gregory A. NORTHROP

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US20150214064A1

公开(公告)日：2015-07-30

申请号：US14167071

申请日：2014-01-29

Applicant: Globalfoundries Inc.

Inventor： David PRITCHARD ,  Jason E. STEPHENS

IPC: H01L21/308 ,  H01L21/28

CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method is provided for fabricating cross-coupled line segments for use, for instance, as a hard mask in fabricating cross-coupled gates of two or more transistors. Fabricating the structure includes: providing a sacrificial mandrel on the substrate, the sacrificial mandrel including a transverse gap through the mandrel separating the sacrificial mandrel into a first mandrel portion and a second mandrel portion; providing a sidewall spacer along sidewalls of the sacrificial mandrel, where sidewall spacers along sidewalls of the first mandrel portion and the second mandrel portion merge within the transverse gap and form a crossbar; and removing the sacrificial mandrel and selectively cutting the sidewall spacers to define the cross-coupled line segments from the sidewall spacers and crossbar. The transverse gap may be provided by directly printing the first and second mandrel portions spaced apart, or by cutting the sacrificial mandrel to provide the gap.

Abstract translation: 提供了一种用于制造用于例如在制造两个或更多个晶体管的交叉耦合栅极中的硬掩模使用的交叉耦合线段的方法。 制造结构包括：在基底上提供牺牲心轴，所述牺牲心轴包括穿过所述心轴的横向间隙，将所述牺牲心轴分成第一心轴部分和第二心轴部分; 沿着所述牺牲心轴的侧壁提供侧壁间隔件，其中沿着所述第一心轴部分的侧壁和所述第二心轴部分的侧壁间隔在所述横向间隙内合并形成横杆; 并且移除牺牲心轴并选择性地切割侧壁间隔件以限定来自侧壁间隔件和横杆的交叉耦合线段。 横向间隙可以通过直接打印间隔开的第一和第二心轴部分，或者通过切割牺牲心轴来提供间隙来提供。

公开(公告)号：US20190267281A1

公开(公告)日：2019-08-29

申请号：US16411775

申请日：2019-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung CHEN ,  Martin J. O'TOOLE ,  Terry A. SPOONER ,  Jason E. STEPHENS

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/033 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.

公开(公告)号：US20190221474A1

公开(公告)日：2019-07-18

申请号：US15872314

申请日：2018-01-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung CHEN ,  Martin J. O'TOOLE ,  Terry A. SPOONER ,  Jason E. STEPHENS

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/033

CPC classification number: H01L21/76816 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53271

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.

公开(公告)号：US20150287604A1

公开(公告)日：2015-10-08

申请号：US14246197

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason E. STEPHENS ,  Lei YUAN ,  Lixia LEI ,  David PRITCHARD ,  Tuhin Guha NEOGI

IPC: H01L21/28

CPC classification number: H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.

Abstract translation: 提供了一种用于在晶片上制造交叉耦合线段以用于例如制造两个或多个晶体管的交叉耦合栅极的方法。 该制造包括：使用第一掩模使具有第一侧面突起的第一线段图案化; 以及使用第二掩模用第二侧面突起构图第二线段。 第二线段与第一线段偏移，并且图案化的第二侧突起覆盖图案化的第一侧突起，并且有助于限定连接第一和第二线段的十字绣线段。 该方法还包括在限定来自第一和第二线段和十字绣段的交叉耦合线段时选择性地切割第一和第二线段。