公开(公告)号：US09478600B2

公开(公告)日：2016-10-25

申请号：US14175587

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

公开(公告)号：US09412640B2

公开(公告)日：2016-08-09

申请号：US13749830

申请日：2013-01-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Karen A. Nummy ,  Ravi M. Todi

IPC: H01L21/44 ,  H01L21/74 ,  H01L29/94

CPC classification number: H01L21/743 ,  H01L29/945

Abstract: A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench;removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate.

Abstract translation: 公开了一种在半导体器件上形成接触的方法。 所述方法包括：在所述半导体器件上形成掩模，所述掩模暴露设置在所述半导体器件的衬底中的沟槽内的至少一个接触节点; 在所述半导体器件上执行第一衬底接触蚀刻，所述第一衬底接触蚀刻凹陷所述沟槽内的所述暴露的接触节点; 去除设置在暴露的接触节点之上和沟槽的侧面上的一组节点膜; 以及在所述暴露的接触节点之上的所述沟槽内形成接触区域，所述接触区域接触所述衬底。

公开(公告)号：US09461042B2

公开(公告)日：2016-10-04

申请号：US14746017

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

公开(公告)号：US09379177B2

公开(公告)日：2016-06-28

申请号：US14684533

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/84 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L28/60 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181

Abstract: A deep trench capacitor structure including an SOI substrate comprising an SOI layer, a rare earth oxide layer, and a bulk substrate, the rare earth oxide layer is located below the SOI layer and above the bulk substrate, and the rare earth oxide layer insulates the SOI layer from the bulk substrate, and a deep trench capacitor extending from a top surface of the SOI layer, through the rare earth oxide layer, down to a location within the bulk substrate, the rare earth oxide layer contacts the deep trench capacitor at an interface between the rare earth oxide layer and the bulk substrate forming an incline away from the deep trench capacitor.

Abstract translation: 包括SOI层，稀土氧化物层和体基板的SOI衬底的深沟槽电容器结构，所述稀土氧化物层位于所述SOI层的下方并且位于所述本体衬底的上方，并且所述稀土氧化物层绝缘 SOI层，以及从SOI层的顶表面延伸穿过稀土氧化物层的深沟槽电容器，到达本体衬底内的位置，稀土氧化物层在 稀土氧化物层与本体衬底之间的界面形成远离深沟槽电容器的斜面。

公开(公告)号：US09293520B2

公开(公告)日：2016-03-22

申请号：US13845560

申请日：2013-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC: H01L21/70 ,  H01L49/02 ,  H01L21/762 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

Abstract translation: 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。