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    DEVICES FORMED BY PERFORMING A COMMON ETCH PATTERNING PROCESS TO FORM GATE AND SOURCE/DRAIN CONTACT OPENINGS
    1.
    发明申请
    DEVICES FORMED BY PERFORMING A COMMON ETCH PATTERNING PROCESS TO FORM GATE AND SOURCE/DRAIN CONTACT OPENINGS 审中-公开
    通过执行常见蚀刻方法形成门窗和源/漏液接触开口形成的装置

    公开(公告)号：US20160190263A1

    公开(公告)日：2016-06-30

    申请号：US15053640

    申请日：2016-02-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  William J. Taylor ,  Min Gyu Sung

    IPC: H01L29/417

    CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653

    Abstract: A device includes an isolation region that defines an active region in a semiconducting substrate and a gate structure, wherein the gate structure has an axial length in a long axis direction thereof such that a first portion of the gate structure is positioned above the active region and a second portion of the gate structure is positioned above the isolation region. Additionally, a gate cap layer is positioned above the gate structure, wherein a first portion of the gate cap layer that is positioned above the first portion of the gate structure is thicker than a second portion of the gate cap layer that is positioned above the second portion of the gate structure.

    Abstract translation: 一种器件包括限定半导体衬底和栅极结构中的有源区的隔离区，其中栅极结构在其长轴方向上具有轴向长度，使得栅极结构的第一部分位于有源区上方，并且 栅极结构的第二部分位于隔离区的上方。 另外，栅极覆盖层位于栅极结构的上方，其中位于栅极结构的第一部分之上的栅极覆盖层的第一部分比位于栅极结构的第二部分之上的栅极覆盖层的第二部分更厚 部分门结构。

    Buried source-drain contact for integrated circuit transistor devices and method of making same
    3.
    发明授权
    Buried source-drain contact for integrated circuit transistor devices and method of making same 有权
    集成电路晶体管器件的埋地源极 - 漏极接触及其制作方法

    公开(公告)号：US09385201B2

    公开(公告)日：2016-07-05

    申请号：US14297822

    申请日：2014-06-06

    Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

    Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

    IPC: H01L21/84 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

    Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
    5.
    发明申请
    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME 有权
    用于集成电路晶体管器件的引出源漏极触点及其制造方法

    公开(公告)号：US20160284599A1

    公开(公告)日：2016-09-29

    申请号：US15179620

    申请日：2016-06-10

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

    Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

    IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/84

    CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

    Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地被金属材料填充以形成埋在衬底中的源极（或漏极）触点。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
    6.
    发明申请
    BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME 有权
    用于集成电路晶体管器件的引出源漏极触点及其制造方法

    公开(公告)号：US20150357425A1

    公开(公告)日：2015-12-10

    申请号：US14297822

    申请日：2014-06-06

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

    IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

    Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

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