公开(公告)号：US11522131B2

公开(公告)日：2022-12-06

申请号：US16945058

申请日：2020-07-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Curtis Chun-I Hsieh ,  Wanbing Yi ,  Benfu Lin ,  Cing Gie Lim ,  Wei-Hui Hsu ,  Juan Boon Tan

IPC: H01L45/00 ,  H01L21/306 ,  H01L27/24

Abstract: An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.

公开(公告)号：US11335635B2

公开(公告)日：2022-05-17

申请号：US16842956

申请日：2020-04-08

Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Inventor： Benfu Lin ,  Kah Wee Gan ,  Cing Gie Lim ,  Chengang Feng

IPC: H01L23/522 ,  H01L25/04

Abstract: A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.

公开(公告)号：US10475990B2

公开(公告)日：2019-11-12

申请号：US15877044

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Curtis Chun-I Hsieh ,  Lup San Leong ,  Wanbing Yi ,  Cing Gie Lim ,  Yi Jiang ,  Juan Boon Tan

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.

公开(公告)号：US20220037590A1

公开(公告)日：2022-02-03

申请号：US16945058

申请日：2020-07-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Curtis Chun-I Hsieh ,  Wanbing Yi ,  Benfu Lin ,  Cing Gie Lim ,  Wei-Hui Hsu ,  Juan Boon Tan

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/306

Abstract: An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.