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87 条记录 (耗时 0.024 秒)

    Resistive random access memory devices
    3.
    发明授权
    Resistive random access memory devices 有权

    公开(公告)号：US11515475B2

    公开(公告)日：2022-11-29

    申请号：US15931607

    申请日：2020-05-14

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Curtis Chun-I Hsieh ,  Wei-Hui Hsu ,  Wanbing Yi ,  Yi Jiang ,  Kai Kang ,  Juan Boon Tan

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

    Memory devices and methods of forming memory devices
    4.
    发明授权
    Memory devices and methods of forming memory devices 有权

    公开(公告)号：US11081523B1

    公开(公告)日：2021-08-03

    申请号：US15931623

    申请日：2020-05-14

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Curtis Chun-I Hsieh ,  Wei-Hui Hsu ,  Yi Jiang ,  Wanbing Yi ,  Juan Boon Tan

    IPC分类号： H01L27/24 ,  G11C13/00 ,  H01L45/00

    摘要： A memory device may be provided, including a base layer, an insulating layer, a first electrode, a switching element, a capping element and a second electrode. The insulating layer may be arranged over the base layer and may include a recess having opposing side walls. The first electrode may be arranged at least partially within the recess of the insulating layer and along the opposing side walls of the recess of the insulating layer. The switching element may be arranged at least partially within the recess of the insulating layer and along the first electrode. The capping element and the second electrode may be arranged at least partially within the recess of the insulating layer. The capping element may be arranged between the second electrode and the switching element, and a part of the second electrode may extend across the capping element to contact the switching element.

    Integrated circuits with integrated memory structures and capacitors and methods for fabricating the same
    6.
    发明授权
    Integrated circuits with integrated memory structures and capacitors and methods for fabricating the same 有权

    公开(公告)号：US10734444B1

    公开(公告)日：2020-08-04

    申请号：US16259549

    申请日：2019-01-28

    申请人： Globalfoundries Singapore Pte. Ltd.

    发明人： Yi Jiang ,  Curtis Chun-I Hsieh ,  Wanbing Yi ,  Juan Boon Tan

    IPC分类号： H01L27/22 ,  H01L49/02 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    摘要： Integrated circuits with integrated memory devices and high capacitors, and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming, from a lower conductive layer, a lower memory interconnect and a lower capacitor interconnects over a substrate. The method further includes forming a conductive memory via coupled to the lower memory interconnect and a conductive capacitor vias coupled to the lower capacitor interconnect. Also, the method includes forming a memory structure over the memory via and forming a capacitor dielectric layer over the memory structure and over the capacitor via. Further, the method includes forming, from an upper conductive layer, an upper memory interconnect coupled to the memory structure and an upper capacitor interconnects over the capacitor dielectric layer over the capacitor via. The capacitor via, capacitor dielectric layer, and upper capacitor interconnects form the high capacitor.

    Integrated circuit with memory cells having reliable interconnection
    8.
    发明授权
    Integrated circuit with memory cells having reliable interconnection 有权

    公开(公告)号：US10580968B1

    公开(公告)日：2020-03-03

    申请号：US16159772

    申请日：2018-10-15

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Wanbing Yi ,  Curtis Chun-I Hsieh ,  Yi Jiang ,  Juan Boon Tan

    IPC分类号： H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L27/12

    摘要： In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region and a second region. The first region includes a memory region having at least one magnetic tunnel junction (MTJ) stack, and the second region includes a logic region. An encapsulation stack is formed in the first and second regions and over the MTJ stack(s). The encapsulation stack includes a first layer, a second layer, and a third layer. A single etch may remove at least a portion of the third layer, the second layer, and the first layer of the encapsulation stack to form a self-aligned MTJ via opening over the at least one MTJ stack to form one or more peaks from the encapsulation stack above or around the MTJ stack.

    MRAM chip magnetic shielding
    9.
    发明授权
    MRAM chip magnetic shielding 有权

    公开(公告)号：US10510946B2

    公开(公告)日：2019-12-17

    申请号：US15080562

    申请日：2016-03-24

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Bharat Bhushan ,  Juan Boon Tan ,  Wanbing Yi ,  Danny Pak-Chum Shum ,  Shan Gao ,  Kangho Lee

    IPC分类号： H01L43/02 ,  H01L43/12

    摘要： Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed. The method includes providing a magnetic shield at the front side of the chip, back side of the chip, and also in the deep trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the prime die region. Magnetic shield in the deep trenches connects front side and back side magnetic shield. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the prime die region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.