公开(公告)号：US11742283B2

公开(公告)日：2023-08-29

申请号：US17139117

申请日：2020-12-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kah Wee Gan ,  Benfu Lin ,  Yun Ling Tan

IPC: H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L28/20 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes a memory device in back end of line (BEOL) materials and a thin film resistor located in the BEOL materials. The thin film resistor includes electrical resistive material, and an insulator material over the electrical resistive material is thicker than insulator material over the memory device.

公开(公告)号：US11335635B2

公开(公告)日：2022-05-17

申请号：US16842956

申请日：2020-04-08

Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Inventor： Benfu Lin ,  Kah Wee Gan ,  Cing Gie Lim ,  Chengang Feng

IPC: H01L23/522 ,  H01L25/04

Abstract: A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.

公开(公告)号：US20240413162A1

公开(公告)日：2024-12-12

申请号：US18332147

申请日：2023-06-09

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Kah Wee Gan ,  Xuesong Rao ,  Wensheng Deng ,  Kemao Lin

IPC: H01L27/12 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a transistor including source/drain regions and a gate, the gate having a gate body. An etch stop layer is over the source/drain regions but not over the gate body. An interconnect layer is over the transistor and includes a dielectric layer. A cavity extends partially through the interconnect layer above the gate, and a portion of the dielectric layer is over the gate body and defines a bottom of the cavity. The cavity provides a mechanism to reduce both on-resistance and off-capacitance for applications such as radio frequency switches.

公开(公告)号：US09842989B2

公开(公告)日：2017-12-12

申请号：US15057107

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Taiebeh Tahmasebi ,  Kah Wee Gan ,  Chim Seng Seet

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetic memory having a base layer with a wetting layer and seed layer is disclosed. The wetting layer and seed layer promotes FCC structure along the (111) orientation to improve PMA. The seed layer includes first and second seed layer separated by a surface smoother, such as a surfactant layer. This enhances the smoothness of the seed layer, resulting in smoother interface in the MTJ stack, which leads to improved thermal endurance.

公开(公告)号：US20210028349A1

公开(公告)日：2021-01-28

申请号：US16521172

申请日：2019-07-24

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Kah Wee Gan ,  Benfu Lin ,  Chim Seng Seet

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a contact overlying a substrate, and a bottom electrode overlying the contact. The bottom electrode is in electrical communication with the contact, and the bottom electrode has a bottom electrode upper surface with a bottom electrode upper surface area. A magnetic tunnel junction memory cell overlies the bottom electrode and is in electrical communication with the bottom electrode. The magnetic tunnel junction memory cell has an MTJ bottom surface with an MTJ bottom surface area that is greater than the bottom electrode surface area.

公开(公告)号：US10468457B1

公开(公告)日：2019-11-05

申请号：US16027716

申请日：2018-07-05

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Dinggui Zeng ,  Kah Wee Gan ,  Kazutaka Yamane

IPC: G11C11/00 ,  H01L27/22 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The spin transfer torque magnetic random access memory structure further includes a fixed layer over the base layer. The fixed layer includes anti-parallel layers including cobalt tungsten/platinum (CoW/Pt) bilayers, cobalt molybdenum/platinum (CoMo/Pt) bilayers, or bilayers including a combination of at least two materials selected from cobalt (Co), tungsten (W), molybdenum (Mo), platinum (Pt), palladium (Pd) or iridium (Ir). Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the fixed layer and a top electrode over the MTJ element.