公开(公告)号：US10978510B2

公开(公告)日：2021-04-13

申请号：US16443255

申请日：2019-06-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Pinghui Li ,  Haiqing Zhou ,  Liying Zhang ,  Wanbing Yi ,  Ming Zhu ,  Danny Pak-Chum Shum ,  Darin Chan

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C5/02 ,  G11C11/16 ,  H01L27/02 ,  H01L43/12 ,  G11C11/15

Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

公开(公告)号：US10374005B2

公开(公告)日：2019-08-06

申请号：US15858655

申请日：2017-12-29

Applicant: GLOBALFOUNDRIES Singapore Pte. ltd.

Inventor： Pinghui Li ,  Haiqing Zhou ,  Liying Zhang ,  Wanbing Yi ,  Ming Zhu ,  Danny Pak-Chum Shum ,  Darin Chan

IPC: G11C5/02 ,  H01L27/02 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

公开(公告)号：US09825185B1

公开(公告)日：2017-11-21

申请号：US15383048

申请日：2016-12-19

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Pinghui Li ,  Ming Zhu ,  Xinshu Cai ,  Fan Zhang ,  Danny Pak-Chum Shum ,  Darin Chan

IPC: H01L29/788 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L23/522 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7885 ,  H01L21/28273 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7838

Abstract: Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures are provided. An exemplary integrated circuit includes a semiconductor substrate having a central semiconductor-on-insulator (SOI) region between first and second non-SOI regions. The substrate includes a semiconductor base in the SOI region and the non-SOI regions, an insulator layer overlying the semiconductor base in the SOI region, and an upper semiconductor layer overlying the insulator layer in the SOI region. The integrated circuit further includes a first conductivity type well formed in the base in the first region and in a first portion of the SOI region, and a second conductivity type well formed in the base in the second region and in a second portion of the SOI region lateral of the first conductivity type well. Also, the integrated circuit includes a non-volatile memory device structure overlying the upper semiconductor layer in the SOI region.

公开(公告)号：US09698200B2

公开(公告)日：2017-07-04

申请号：US15287771

申请日：2016-10-07

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Pinghui Li ,  Ming Zhu ,  Shunqiang Gong ,  Wanbing Yi ,  Darin Chan ,  Yiang Aun Nga

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C5/025 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

公开(公告)号：US09780231B1

公开(公告)日：2017-10-03

申请号：US15271528

申请日：2016-09-21

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Pinghui Li ,  Ming Zhu ,  Danny Pak-Chum Shum ,  Xinshu Cai ,  Darin Chan

IPC: H01L29/788 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7881 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/66825 ,  H01L29/7883

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a handle layer. A partial buried insulator overlies the handle layer and underlies the active layer, terminates at a buried insulator termination point, and includes an electrically insulating material. A substrate extension is adjacent to the partial buried insulator, where the substrate extension overlies the handle layer and underlies the active layer, and where the substrate extension directly contacts the partial buried insulator at the buried insulator termination point. The substrate extension includes a semiconductive material. A memory gate overlies the active layer.